forked from ShuriZma/suyu
shader_ir/decode: Implement AOFFI for TEX and TLD4
This commit is contained in:
ReinUsesLisp
parent
cf4ecc1945
commit
cb68ce7c2f
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@ -7,7 +7,9 @@
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#include <fmt/format.h>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/shader_ir.h"
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@ -41,19 +43,18 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::TEX: {
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UNIMPLEMENTED_IF_MSG(instr.tex.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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if (instr.tex.UsesMiscMode(TextureMiscMode::NODEP)) {
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LOG_WARNING(HW_GPU, "TEX.NODEP implementation is incomplete");
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}
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const TextureType texture_type{instr.tex.texture_type};
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const bool is_array = instr.tex.array != 0;
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const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI);
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const bool depth_compare = instr.tex.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.tex.GetTextureProcessMode();
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WriteTexInstructionFloat(
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bb, instr, GetTexCode(instr, texture_type, process_mode, depth_compare, is_array));
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bb, instr,
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GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, is_aoffi));
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break;
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}
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case OpCode::Id::TEXS: {
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@ -78,8 +79,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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}
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case OpCode::Id::TLD4: {
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ASSERT(instr.tld4.array == 0);
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UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::NDV),
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"NDV is not implemented");
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UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::PTP),
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@ -92,8 +91,9 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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const auto texture_type = instr.tld4.texture_type.Value();
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const bool depth_compare = instr.tld4.UsesMiscMode(TextureMiscMode::DC);
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const bool is_array = instr.tld4.array != 0;
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WriteTexInstructionFloat(bb, instr,
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GetTld4Code(instr, texture_type, depth_compare, is_array));
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const bool is_aoffi = instr.tld4.UsesMiscMode(TextureMiscMode::AOFFI);
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WriteTexInstructionFloat(
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bb, instr, GetTld4Code(instr, texture_type, depth_compare, is_array, is_aoffi));
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break;
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}
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case OpCode::Id::TLD4S: {
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@ -127,7 +127,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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Node4 values;
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for (u32 element = 0; element < values.size(); ++element) {
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auto coords_copy = coords;
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MetaTexture meta{sampler, {}, {}, {}, {}, component, element};
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MetaTexture meta{sampler, {}, {}, {}, {}, {}, component, element};
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values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy));
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}
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@ -152,7 +152,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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if (!instr.txq.IsComponentEnabled(element)) {
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continue;
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}
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MetaTexture meta{sampler, {}, {}, {}, {}, {}, element};
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MetaTexture meta{sampler, {}, {}, {}, {}, {}, {}, element};
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const Node value =
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Operation(OperationCode::TextureQueryDimensions, meta, GetRegister(instr.gpr8));
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SetTemporal(bb, indexer++, value);
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@ -202,7 +202,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
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for (u32 element = 0; element < 2; ++element) {
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auto params = coords;
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MetaTexture meta{sampler, {}, {}, {}, {}, {}, element};
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MetaTexture meta{sampler, {}, {}, {}, {}, {}, {}, element};
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const Node value = Operation(OperationCode::TextureQueryLod, meta, std::move(params));
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SetTemporal(bb, element, value);
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}
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@ -325,7 +325,8 @@ void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr,
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Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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TextureProcessMode process_mode, std::vector<Node> coords,
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Node array, Node depth_compare, u32 bias_offset) {
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Node array, Node depth_compare, u32 bias_offset,
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std::vector<Node> aoffi) {
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const bool is_array = array;
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const bool is_shadow = depth_compare;
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@ -374,7 +375,7 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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Node4 values;
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for (u32 element = 0; element < values.size(); ++element) {
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auto copy_coords = coords;
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MetaTexture meta{sampler, array, depth_compare, bias, lod, {}, element};
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MetaTexture meta{sampler, array, depth_compare, aoffi, bias, lod, {}, element};
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values[element] = Operation(read_method, meta, std::move(copy_coords));
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}
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@ -382,9 +383,15 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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}
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Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
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TextureProcessMode process_mode, bool depth_compare, bool is_array) {
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const bool lod_bias_enabled =
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(process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ);
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TextureProcessMode process_mode, bool depth_compare, bool is_array,
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bool is_aoffi) {
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const bool lod_bias_enabled{
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(process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ)};
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u64 parameter_register = instr.gpr20.Value();
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if (lod_bias_enabled) {
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++parameter_register;
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}
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const auto [coord_count, total_coord_count] = ValidateAndGetCoordinateElement(
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texture_type, depth_compare, is_array, lod_bias_enabled, 4, 5);
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@ -404,15 +411,19 @@ Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
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const Node array = is_array ? GetRegister(array_register) : nullptr;
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std::vector<Node> aoffi;
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if (is_aoffi) {
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aoffi = GetAoffiCoordinates(GetRegister(parameter_register++), coord_count, false);
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}
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Node dc{};
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if (depth_compare) {
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// Depth is always stored in the register signaled by gpr20 or in the next register if lod
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// or bias are used
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const u64 depth_register = instr.gpr20.Value() + (lod_bias_enabled ? 1 : 0);
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dc = GetRegister(depth_register);
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dc = GetRegister(parameter_register++);
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}
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return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, 0);
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return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, 0, aoffi);
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}
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Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
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@ -448,11 +459,11 @@ Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
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dc = GetRegister(depth_register);
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}
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return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, bias_offset);
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return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, bias_offset, {});
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}
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Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare,
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bool is_array) {
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bool is_array, bool is_aoffi) {
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const std::size_t coord_count = GetCoordCount(texture_type);
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const std::size_t total_coord_count = coord_count + (is_array ? 1 : 0);
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const std::size_t total_reg_count = total_coord_count + (depth_compare ? 1 : 0);
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@ -463,15 +474,27 @@ Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool de
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const u64 coord_register = array_register + (is_array ? 1 : 0);
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std::vector<Node> coords;
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for (size_t i = 0; i < coord_count; ++i)
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for (std::size_t i = 0; i < coord_count; ++i) {
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coords.push_back(GetRegister(coord_register + i));
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}
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u64 parameter_register = instr.gpr20.Value();
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std::vector<Node> aoffi;
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if (is_aoffi) {
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aoffi = GetAoffiCoordinates(GetRegister(parameter_register++), coord_count, true);
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}
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Node dc{};
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if (depth_compare) {
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dc = GetRegister(parameter_register++);
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}
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const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, depth_compare);
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Node4 values;
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for (u32 element = 0; element < values.size(); ++element) {
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auto coords_copy = coords;
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MetaTexture meta{sampler, GetRegister(array_register), {}, {}, {}, {}, element};
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MetaTexture meta{sampler, GetRegister(array_register), dc, aoffi, {}, {}, {}, element};
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values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy));
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}
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@ -507,7 +530,7 @@ Node4 ShaderIR::GetTldsCode(Instruction instr, TextureType texture_type, bool is
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Node4 values;
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for (u32 element = 0; element < values.size(); ++element) {
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auto coords_copy = coords;
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MetaTexture meta{sampler, array, {}, {}, lod, {}, element};
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MetaTexture meta{sampler, array, {}, {}, {}, lod, {}, element};
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values[element] = Operation(OperationCode::TexelFetch, meta, std::move(coords_copy));
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}
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return values;
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@ -531,4 +554,45 @@ std::tuple<std::size_t, std::size_t> ShaderIR::ValidateAndGetCoordinateElement(
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return {coord_count, total_coord_count};
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}
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std::vector<Node> ShaderIR::GetAoffiCoordinates(Node aoffi_reg, std::size_t coord_count,
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bool is_tld4) {
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const auto [coord_offsets, size, wrap_value,
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diff_value] = [is_tld4]() -> std::tuple<std::array<u32, 3>, u32, s32, s32> {
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if (is_tld4) {
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return {{0, 8, 16}, 6, 32, 64};
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} else {
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return {{0, 4, 8}, 4, 8, 16};
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}
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}();
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const u32 mask = (1 << size) - 1;
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std::vector<Node> aoffi;
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aoffi.reserve(coord_count);
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const auto aoffi_immediate{
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TrackImmediate(aoffi_reg, global_code, static_cast<s64>(global_code.size()))};
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if (!aoffi_immediate) {
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// Variable access, not supported on AMD.
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LOG_WARNING(HW_GPU,
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"AOFFI constant folding failed, some hardware might have graphical issues");
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for (std::size_t coord = 0; coord < coord_count; ++coord) {
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const Node value = BitfieldExtract(aoffi_reg, coord_offsets.at(coord), size);
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const Node condition =
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Operation(OperationCode::LogicalIGreaterEqual, value, Immediate(wrap_value));
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const Node negative = Operation(OperationCode::IAdd, value, Immediate(-diff_value));
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aoffi.push_back(Operation(OperationCode::Select, condition, negative, value));
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}
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return aoffi;
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}
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for (std::size_t coord = 0; coord < coord_count; ++coord) {
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s32 value = (*aoffi_immediate >> coord_offsets.at(coord)) & mask;
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if (value >= wrap_value) {
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value -= diff_value;
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}
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aoffi.push_back(Immediate(value));
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}
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return aoffi;
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}
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} // namespace VideoCommon::Shader
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@ -291,6 +291,7 @@ struct MetaTexture {
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const Sampler& sampler;
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Node array{};
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Node depth_compare{};
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std::vector<Node> aoffi;
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Node bias{};
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Node lod{};
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Node component{};
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@ -742,14 +743,14 @@ private:
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Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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bool is_array);
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bool is_array, bool is_aoffi);
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Node4 GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
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bool is_array);
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Node4 GetTld4Code(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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bool depth_compare, bool is_array);
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bool depth_compare, bool is_array, bool is_aoffi);
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Node4 GetTldsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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bool is_array);
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@ -758,9 +759,11 @@ private:
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Tegra::Shader::TextureType texture_type, bool depth_compare, bool is_array,
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bool lod_bias_enabled, std::size_t max_coords, std::size_t max_inputs);
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std::vector<Node> GetAoffiCoordinates(Node aoffi_reg, std::size_t coord_count, bool is_tld4);
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Node4 GetTextureCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
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Tegra::Shader::TextureProcessMode process_mode, std::vector<Node> coords,
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Node array, Node depth_compare, u32 bias_offset);
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Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi);
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Node GetVideoOperand(Node op, bool is_chunk, bool is_signed, Tegra::Shader::VideoType type,
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u64 byte_height);
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