forked from ShuriZma/suyu
fixed_pipeline_state: Pack attribute state
Reduce FixedPipelineState's size from 1384 to 664 bytes
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2133482a17
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ab6704f20c
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@ -1149,7 +1149,7 @@ public:
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/// Returns whether the vertex array specified by index is supposed to be
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/// accessed per instance or not.
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bool IsInstancingEnabled(u32 index) const {
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bool IsInstancingEnabled(std::size_t index) const {
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return is_instanced[index];
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}
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} instanced_arrays;
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@ -6,6 +6,7 @@
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#include <boost/functional/hash.hpp>
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#include "common/cityhash.h"
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#include "common/common_types.h"
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#include "video_core/renderer_vulkan/fixed_pipeline_state.h"
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@ -128,25 +129,6 @@ constexpr FixedPipelineState::Rasterizer GetRasterizerState(const Maxwell& regs)
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} // Anonymous namespace
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std::size_t FixedPipelineState::VertexBinding::Hash() const noexcept {
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return (index << stride) ^ divisor;
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}
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bool FixedPipelineState::VertexBinding::operator==(const VertexBinding& rhs) const noexcept {
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return std::tie(index, stride, divisor) == std::tie(rhs.index, rhs.stride, rhs.divisor);
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}
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std::size_t FixedPipelineState::VertexAttribute::Hash() const noexcept {
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return static_cast<std::size_t>(index) ^ (static_cast<std::size_t>(buffer) << 13) ^
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(static_cast<std::size_t>(type) << 22) ^ (static_cast<std::size_t>(size) << 31) ^
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(static_cast<std::size_t>(offset) << 36);
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}
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bool FixedPipelineState::VertexAttribute::operator==(const VertexAttribute& rhs) const noexcept {
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return std::tie(index, buffer, type, size, offset) ==
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std::tie(rhs.index, rhs.buffer, rhs.type, rhs.size, rhs.offset);
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}
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std::size_t FixedPipelineState::StencilFace::Hash() const noexcept {
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return static_cast<std::size_t>(action_stencil_fail) ^
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(static_cast<std::size_t>(action_depth_fail) << 4) ^
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@ -182,21 +164,12 @@ bool FixedPipelineState::BlendingAttachment::operator==(const BlendingAttachment
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}
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std::size_t FixedPipelineState::VertexInput::Hash() const noexcept {
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std::size_t hash = num_bindings ^ (num_attributes << 32);
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for (std::size_t i = 0; i < num_bindings; ++i) {
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boost::hash_combine(hash, bindings[i].Hash());
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}
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for (std::size_t i = 0; i < num_attributes; ++i) {
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boost::hash_combine(hash, attributes[i].Hash());
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}
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return hash;
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// TODO(Rodrigo): Replace this
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return Common::CityHash64(reinterpret_cast<const char*>(this), sizeof *this);
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}
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bool FixedPipelineState::VertexInput::operator==(const VertexInput& rhs) const noexcept {
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return std::equal(bindings.begin(), bindings.begin() + num_bindings, rhs.bindings.begin(),
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rhs.bindings.begin() + rhs.num_bindings) &&
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std::equal(attributes.begin(), attributes.begin() + num_attributes,
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rhs.attributes.begin(), rhs.attributes.begin() + rhs.num_attributes);
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return std::memcmp(this, &rhs, sizeof *this) == 0;
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}
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std::size_t FixedPipelineState::InputAssembly::Hash() const noexcept {
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@ -7,6 +7,7 @@
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#include <array>
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#include <type_traits>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "video_core/engines/maxwell_3d.h"
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@ -18,48 +19,11 @@ using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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// TODO(Rodrigo): Optimize this structure.
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template <class T>
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inline constexpr bool IsHashable = std::has_unique_object_representations_v<T>&&
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std::is_trivially_copyable_v<T>&& std::is_trivially_constructible_v<T>;
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struct FixedPipelineState {
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using PixelFormat = VideoCore::Surface::PixelFormat;
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struct VertexBinding {
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constexpr VertexBinding(u32 index, u32 stride, u32 divisor)
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: index{index}, stride{stride}, divisor{divisor} {}
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VertexBinding() = default;
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u32 index;
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u32 stride;
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u32 divisor;
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std::size_t Hash() const noexcept;
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bool operator==(const VertexBinding& rhs) const noexcept;
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bool operator!=(const VertexBinding& rhs) const noexcept {
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return !operator==(rhs);
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}
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};
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struct VertexAttribute {
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constexpr VertexAttribute(u32 index, u32 buffer, Maxwell::VertexAttribute::Type type,
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Maxwell::VertexAttribute::Size size, u32 offset)
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: index{index}, buffer{buffer}, type{type}, size{size}, offset{offset} {}
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VertexAttribute() = default;
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u32 index;
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u32 buffer;
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Maxwell::VertexAttribute::Type type;
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Maxwell::VertexAttribute::Size size;
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u32 offset;
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std::size_t Hash() const noexcept;
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bool operator==(const VertexAttribute& rhs) const noexcept;
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bool operator!=(const VertexAttribute& rhs) const noexcept {
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return !operator==(rhs);
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}
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};
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struct StencilFace {
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constexpr StencilFace(Maxwell::StencilOp action_stencil_fail,
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Maxwell::StencilOp action_depth_fail,
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@ -114,10 +78,52 @@ struct FixedPipelineState {
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};
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struct VertexInput {
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std::size_t num_bindings = 0;
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std::size_t num_attributes = 0;
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std::array<VertexBinding, Maxwell::NumVertexArrays> bindings;
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std::array<VertexAttribute, Maxwell::NumVertexAttributes> attributes;
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union Binding {
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u16 raw;
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BitField<0, 1, u16> enabled;
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BitField<1, 12, u16> stride;
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};
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union Attribute {
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u32 raw;
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BitField<0, 1, u32> enabled;
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BitField<1, 5, u32> buffer;
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BitField<6, 14, u32> offset;
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BitField<20, 3, u32> type;
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BitField<23, 6, u32> size;
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constexpr Maxwell::VertexAttribute::Type Type() const noexcept {
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return static_cast<Maxwell::VertexAttribute::Type>(type.Value());
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}
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constexpr Maxwell::VertexAttribute::Size Size() const noexcept {
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return static_cast<Maxwell::VertexAttribute::Size>(size.Value());
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}
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};
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std::array<Binding, Maxwell::NumVertexArrays> bindings;
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std::array<u32, Maxwell::NumVertexArrays> binding_divisors;
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std::array<Attribute, Maxwell::NumVertexAttributes> attributes;
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void SetBinding(std::size_t index, bool enabled, u32 stride, u32 divisor) noexcept {
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auto& binding = bindings[index];
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binding.raw = 0;
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binding.enabled.Assign(enabled ? 1 : 0);
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binding.stride.Assign(stride);
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binding_divisors[index] = divisor;
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}
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void SetAttribute(std::size_t index, bool enabled, u32 buffer, u32 offset,
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Maxwell::VertexAttribute::Type type,
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Maxwell::VertexAttribute::Size size) noexcept {
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auto& attribute = attributes[index];
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attribute.raw = 0;
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attribute.enabled.Assign(enabled ? 1 : 0);
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attribute.buffer.Assign(buffer);
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attribute.offset.Assign(offset);
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attribute.type.Assign(static_cast<u32>(type));
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attribute.size.Assign(static_cast<u32>(size));
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}
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std::size_t Hash() const noexcept;
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@ -127,6 +133,7 @@ struct FixedPipelineState {
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return !operator==(rhs);
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}
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};
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static_assert(IsHashable<VertexInput>);
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struct InputAssembly {
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constexpr InputAssembly(Maxwell::PrimitiveTopology topology, bool primitive_restart_enable,
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@ -256,8 +263,6 @@ struct FixedPipelineState {
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DepthStencil depth_stencil;
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ColorBlending color_blending;
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};
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static_assert(std::is_trivially_copyable_v<FixedPipelineState::VertexBinding>);
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static_assert(std::is_trivially_copyable_v<FixedPipelineState::VertexAttribute>);
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static_assert(std::is_trivially_copyable_v<FixedPipelineState::StencilFace>);
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static_assert(std::is_trivially_copyable_v<FixedPipelineState::BlendingAttachment>);
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static_assert(std::is_trivially_copyable_v<FixedPipelineState::VertexInput>);
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@ -165,35 +165,41 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
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std::vector<VkVertexInputBindingDescription> vertex_bindings;
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std::vector<VkVertexInputBindingDivisorDescriptionEXT> vertex_binding_divisors;
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for (std::size_t i = 0; i < vi.num_bindings; ++i) {
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const auto& binding = vi.bindings[i];
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const bool instanced = binding.divisor != 0;
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for (std::size_t index = 0; index < std::size(vi.bindings); ++index) {
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const auto& binding = vi.bindings[index];
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if (!binding.enabled) {
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continue;
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}
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const bool instanced = vi.binding_divisors[index] != 0;
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const auto rate = instanced ? VK_VERTEX_INPUT_RATE_INSTANCE : VK_VERTEX_INPUT_RATE_VERTEX;
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auto& vertex_binding = vertex_bindings.emplace_back();
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vertex_binding.binding = binding.index;
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vertex_binding.binding = static_cast<u32>(index);
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vertex_binding.stride = binding.stride;
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vertex_binding.inputRate = rate;
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if (instanced) {
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auto& binding_divisor = vertex_binding_divisors.emplace_back();
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binding_divisor.binding = binding.index;
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binding_divisor.divisor = binding.divisor;
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binding_divisor.binding = static_cast<u32>(index);
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binding_divisor.divisor = vi.binding_divisors[index];
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}
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}
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std::vector<VkVertexInputAttributeDescription> vertex_attributes;
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const auto& input_attributes = program[0]->entries.attributes;
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for (std::size_t i = 0; i < vi.num_attributes; ++i) {
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const auto& attribute = vi.attributes[i];
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if (input_attributes.find(attribute.index) == input_attributes.end()) {
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for (std::size_t index = 0; index < std::size(vi.attributes); ++index) {
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const auto& attribute = vi.attributes[index];
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if (!attribute.enabled) {
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continue;
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}
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if (input_attributes.find(static_cast<u32>(index)) == input_attributes.end()) {
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// Skip attributes not used by the vertex shaders.
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continue;
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}
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auto& vertex_attribute = vertex_attributes.emplace_back();
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vertex_attribute.location = attribute.index;
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vertex_attribute.location = static_cast<u32>(index);
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vertex_attribute.binding = attribute.buffer;
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vertex_attribute.format = MaxwellToVK::VertexFormat(attribute.type, attribute.size);
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vertex_attribute.format = MaxwellToVK::VertexFormat(attribute.Type(), attribute.Size());
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vertex_attribute.offset = attribute.offset;
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}
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@ -334,7 +334,7 @@ VKPipelineCache::DecompileShaders(const GraphicsPipelineCacheKey& key) {
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specialization.point_size = fixed_state.input_assembly.point_size;
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}
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for (std::size_t i = 0; i < Maxwell::NumVertexAttributes; ++i) {
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specialization.attribute_types[i] = fixed_state.vertex_input.attributes[i].type;
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specialization.attribute_types[i] = fixed_state.vertex_input.attributes[i].Type();
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}
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specialization.ndc_minus_one_to_one = fixed_state.rasterizer.ndc_minus_one_to_one;
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@ -806,25 +806,29 @@ void RasterizerVulkan::SetupVertexArrays(FixedPipelineState::VertexInput& vertex
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BufferBindings& buffer_bindings) {
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const auto& regs = system.GPU().Maxwell3D().regs;
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for (u32 index = 0; index < static_cast<u32>(Maxwell::NumVertexAttributes); ++index) {
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for (std::size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) {
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const auto& attrib = regs.vertex_attrib_format[index];
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if (!attrib.IsValid()) {
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vertex_input.SetAttribute(index, false, 0, 0, {}, {});
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continue;
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}
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const auto& buffer = regs.vertex_array[attrib.buffer];
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[[maybe_unused]] const auto& buffer = regs.vertex_array[attrib.buffer];
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ASSERT(buffer.IsEnabled());
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vertex_input.attributes[vertex_input.num_attributes++] =
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FixedPipelineState::VertexAttribute(index, attrib.buffer, attrib.type, attrib.size,
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attrib.offset);
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vertex_input.SetAttribute(index, true, attrib.buffer, attrib.offset, attrib.type.Value(),
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attrib.size.Value());
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}
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for (u32 index = 0; index < static_cast<u32>(Maxwell::NumVertexArrays); ++index) {
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for (std::size_t index = 0; index < Maxwell::NumVertexArrays; ++index) {
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const auto& vertex_array = regs.vertex_array[index];
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if (!vertex_array.IsEnabled()) {
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vertex_input.SetBinding(index, false, 0, 0);
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continue;
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}
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vertex_input.SetBinding(
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index, true, vertex_array.stride,
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regs.instanced_arrays.IsInstancingEnabled(index) ? vertex_array.divisor : 0);
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const GPUVAddr start{vertex_array.StartAddress()};
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const GPUVAddr end{regs.vertex_array_limit[index].LimitAddress()};
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ASSERT(end > start);
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const std::size_t size{end - start + 1};
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const auto [buffer, offset] = buffer_cache.UploadMemory(start, size);
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vertex_input.bindings[vertex_input.num_bindings++] = FixedPipelineState::VertexBinding(
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index, vertex_array.stride,
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regs.instanced_arrays.IsInstancingEnabled(index) ? vertex_array.divisor : 0);
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buffer_bindings.AddVertexBinding(buffer, offset);
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}
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}
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