forked from ShuriZma/suyu
Merge pull request #3542 from namkazt/patch-10
Implement MME shadow RAM
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commit
7981910746
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@ -98,6 +98,8 @@ void Maxwell3D::InitializeRegisterDefaults() {
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regs.framebuffer_srgb = 1;
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regs.front_face = Maxwell3D::Regs::FrontFace::ClockWise;
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shadow_state = regs;
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mme_inline[MAXWELL3D_REG_INDEX(draw.vertex_end_gl)] = true;
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mme_inline[MAXWELL3D_REG_INDEX(draw.vertex_begin_gl)] = true;
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mme_inline[MAXWELL3D_REG_INDEX(vertex_buffer.count)] = true;
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@ -160,8 +162,17 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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if (regs.reg_array[method] != method_call.argument) {
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regs.reg_array[method] = method_call.argument;
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u32 arg = method_call.argument;
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// Keep track of the register value in shadow_state when requested.
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if (shadow_state.shadow_ram_control == Regs::ShadowRamControl::Track ||
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shadow_state.shadow_ram_control == Regs::ShadowRamControl::TrackWithFilter) {
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shadow_state.reg_array[method] = arg;
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} else if (shadow_state.shadow_ram_control == Regs::ShadowRamControl::Replay) {
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arg = shadow_state.reg_array[method];
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}
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if (regs.reg_array[method] != arg) {
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regs.reg_array[method] = arg;
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for (const auto& table : dirty.tables) {
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dirty.flags[table[method]] = true;
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@ -169,12 +180,16 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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}
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switch (method) {
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case MAXWELL3D_REG_INDEX(shadow_ram_control): {
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shadow_state.shadow_ram_control = static_cast<Regs::ShadowRamControl>(method_call.argument);
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break;
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}
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case MAXWELL3D_REG_INDEX(macros.data): {
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ProcessMacroUpload(method_call.argument);
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ProcessMacroUpload(arg);
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break;
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}
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case MAXWELL3D_REG_INDEX(macros.bind): {
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ProcessMacroBind(method_call.argument);
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ProcessMacroBind(arg);
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break;
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}
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case MAXWELL3D_REG_INDEX(firmware[4]): {
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@ -250,7 +265,7 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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}
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case MAXWELL3D_REG_INDEX(data_upload): {
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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upload_state.ProcessData(arg, is_last_call);
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if (is_last_call) {
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OnMemoryWrite();
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}
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@ -531,6 +531,17 @@ public:
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Fill = 0x1b02,
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};
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enum class ShadowRamControl : u32 {
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// write value to shadow ram
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Track = 0,
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// write value to shadow ram ( with validation ??? )
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TrackWithFilter = 1,
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// only write to real hw register
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Passthrough = 2,
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// write value from shadow ram to real hw register
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Replay = 3,
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};
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struct RenderTargetConfig {
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u32 address_high;
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u32 address_low;
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@ -674,7 +685,9 @@ public:
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u32 bind;
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} macros;
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INSERT_UNION_PADDING_WORDS(0x17);
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ShadowRamControl shadow_ram_control;
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INSERT_UNION_PADDING_WORDS(0x16);
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Upload::Registers upload;
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struct {
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@ -1263,7 +1276,12 @@ public:
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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};
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Regs regs{};
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/// Store temporary hw register values, used by some calls to restore state after a operation
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Regs shadow_state;
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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static_assert(std::is_trivially_copyable_v<Regs>, "Maxwell3D Regs must be trivially copyable");
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@ -1458,6 +1476,7 @@ private:
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(macros, 0x45);
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ASSERT_REG_POSITION(shadow_ram_control, 0x49);
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ASSERT_REG_POSITION(upload, 0x60);
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ASSERT_REG_POSITION(exec_upload, 0x6C);
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ASSERT_REG_POSITION(data_upload, 0x6D);
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