forked from ShuriZma/suyu
core: arm: Implement InvalidateCacheRange for CPU cache invalidation.
This commit is contained in:
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c0870315fd
commit
63fd1bb503
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@ -70,12 +70,19 @@ public:
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/// Clear all instruction cache
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/// Clear all instruction cache
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virtual void ClearInstructionCache() = 0;
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virtual void ClearInstructionCache() = 0;
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/// Notifies CPU emulation that the current page table has changed.
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/**
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///
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* Clear instruction cache range
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/// @param new_page_table The new page table.
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* @param addr Start address of the cache range to clear
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/// @param new_address_space_size_in_bits The new usable size of the address space in bits.
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* @param size Size of the cache range to clear, starting at addr
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/// This can be either 32, 36, or 39 on official software.
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*/
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///
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virtual void InvalidateCacheRange(VAddr addr, std::size_t size) = 0;
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/**
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* Notifies CPU emulation that the current page table has changed.
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* @param new_page_table The new page table.
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* @param new_address_space_size_in_bits The new usable size of the address space in bits.
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* This can be either 32, 36, or 39 on official software.
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*/
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virtual void PageTableChanged(Common::PageTable& new_page_table,
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virtual void PageTableChanged(Common::PageTable& new_page_table,
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std::size_t new_address_space_size_in_bits) = 0;
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std::size_t new_address_space_size_in_bits) = 0;
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@ -286,6 +286,13 @@ void ARM_Dynarmic_32::ClearInstructionCache() {
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jit->ClearCache();
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jit->ClearCache();
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}
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}
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void ARM_Dynarmic_32::InvalidateCacheRange(VAddr addr, std::size_t size) {
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if (!jit) {
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return;
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}
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jit->InvalidateCacheRange(static_cast<u32>(addr), size);
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}
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void ARM_Dynarmic_32::ClearExclusiveState() {
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void ARM_Dynarmic_32::ClearExclusiveState() {
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jit->ClearExclusiveState();
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jit->ClearExclusiveState();
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}
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}
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@ -59,6 +59,7 @@ public:
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void ClearExclusiveState() override;
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void ClearExclusiveState() override;
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void ClearInstructionCache() override;
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void ClearInstructionCache() override;
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void InvalidateCacheRange(VAddr addr, std::size_t size) override;
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void PageTableChanged(Common::PageTable& new_page_table,
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void PageTableChanged(Common::PageTable& new_page_table,
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std::size_t new_address_space_size_in_bits) override;
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std::size_t new_address_space_size_in_bits) override;
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@ -322,6 +322,13 @@ void ARM_Dynarmic_64::ClearInstructionCache() {
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jit->ClearCache();
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jit->ClearCache();
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}
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}
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void ARM_Dynarmic_64::InvalidateCacheRange(VAddr addr, std::size_t size) {
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if (!jit) {
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return;
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}
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jit->InvalidateCacheRange(addr, size);
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}
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void ARM_Dynarmic_64::ClearExclusiveState() {
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void ARM_Dynarmic_64::ClearExclusiveState() {
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jit->ClearExclusiveState();
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jit->ClearExclusiveState();
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}
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}
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@ -56,6 +56,7 @@ public:
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void ClearExclusiveState() override;
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void ClearExclusiveState() override;
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void ClearInstructionCache() override;
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void ClearInstructionCache() override;
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void InvalidateCacheRange(VAddr addr, std::size_t size) override;
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void PageTableChanged(Common::PageTable& new_page_table,
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void PageTableChanged(Common::PageTable& new_page_table,
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std::size_t new_address_space_size_in_bits) override;
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std::size_t new_address_space_size_in_bits) override;
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@ -457,6 +457,10 @@ void System::InvalidateCpuInstructionCaches() {
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impl->kernel.InvalidateAllInstructionCaches();
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impl->kernel.InvalidateAllInstructionCaches();
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}
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}
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void System::InvalidateCpuInstructionCacheRange(VAddr addr, std::size_t size) {
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impl->kernel.InvalidateCpuInstructionCacheRange(addr, size);
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}
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void System::Shutdown() {
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void System::Shutdown() {
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impl->Shutdown();
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impl->Shutdown();
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}
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}
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@ -166,6 +166,8 @@ public:
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*/
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*/
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void InvalidateCpuInstructionCaches();
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void InvalidateCpuInstructionCaches();
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void InvalidateCpuInstructionCacheRange(VAddr addr, std::size_t size);
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/// Shutdown the emulated system.
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/// Shutdown the emulated system.
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void Shutdown();
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void Shutdown();
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@ -497,12 +497,17 @@ const Core::ExclusiveMonitor& KernelCore::GetExclusiveMonitor() const {
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}
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}
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void KernelCore::InvalidateAllInstructionCaches() {
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void KernelCore::InvalidateAllInstructionCaches() {
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if (!IsMulticore()) {
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for (auto& physical_core : impl->cores) {
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for (auto& physical_core : impl->cores) {
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physical_core.ArmInterface().ClearInstructionCache();
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physical_core.ArmInterface().ClearInstructionCache();
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}
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}
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} else {
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}
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UNIMPLEMENTED();
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void KernelCore::InvalidateCpuInstructionCacheRange(VAddr addr, std::size_t size) {
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for (auto& physical_core : impl->cores) {
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if (!physical_core.IsInitialized()) {
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continue;
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}
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physical_core.ArmInterface().InvalidateCacheRange(addr, size);
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}
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}
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}
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}
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@ -156,6 +156,8 @@ public:
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void InvalidateAllInstructionCaches();
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void InvalidateAllInstructionCaches();
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void InvalidateCpuInstructionCacheRange(VAddr addr, std::size_t size);
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/// Adds a port to the named port table
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/// Adds a port to the named port table
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void AddNamedPort(std::string name, std::shared_ptr<ClientPort> port);
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void AddNamedPort(std::string name, std::shared_ptr<ClientPort> port);
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@ -670,6 +670,11 @@ ResultCode PageTable::SetCodeMemoryPermission(VAddr addr, std::size_t size, Memo
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return RESULT_SUCCESS;
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return RESULT_SUCCESS;
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}
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}
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if ((prev_perm & MemoryPermission::Execute) != (perm & MemoryPermission::Execute)) {
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// Memory execution state is changing, invalidate CPU cache range
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system.InvalidateCpuInstructionCacheRange(addr, size);
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}
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const std::size_t num_pages{size / PageSize};
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const std::size_t num_pages{size / PageSize};
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const OperationType operation{(perm & MemoryPermission::Execute) != MemoryPermission::None
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const OperationType operation{(perm & MemoryPermission::Execute) != MemoryPermission::None
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? OperationType::ChangePermissionsAndRefresh
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? OperationType::ChangePermissionsAndRefresh
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@ -58,6 +58,10 @@ public:
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// Shutdown this physical core.
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// Shutdown this physical core.
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void Shutdown();
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void Shutdown();
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bool IsInitialized() const {
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return arm_interface != nullptr;
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}
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Core::ARM_Interface& ArmInterface() {
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Core::ARM_Interface& ArmInterface() {
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return *arm_interface;
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return *arm_interface;
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}
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}
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@ -527,9 +527,6 @@ public:
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header.segment_headers[RO_INDEX].memory_size,
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header.segment_headers[RO_INDEX].memory_size,
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header.segment_headers[DATA_INDEX].memory_size, nro_address});
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header.segment_headers[DATA_INDEX].memory_size, nro_address});
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// Invalidate JIT caches for the newly mapped process code
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system.InvalidateCpuInstructionCaches();
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IPC::ResponseBuilder rb{ctx, 4};
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IPC::ResponseBuilder rb{ctx, 4};
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rb.Push(RESULT_SUCCESS);
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rb.Push(RESULT_SUCCESS);
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rb.Push(*map_result);
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rb.Push(*map_result);
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@ -590,8 +587,6 @@ public:
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const auto result{UnmapNro(iter->second)};
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const auto result{UnmapNro(iter->second)};
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system.InvalidateCpuInstructionCaches();
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nro.erase(iter);
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nro.erase(iter);
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IPC::ResponseBuilder rb{ctx, 2};
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IPC::ResponseBuilder rb{ctx, 2};
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