forked from ShuriZma/suyu
add shader stage when init shader ir
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2cefdd92bd
commit
58bcb86af5
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@ -234,7 +234,7 @@ Shader CachedShader::CreateStageFromMemory(const ShaderParameters& params,
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const std::size_t size_in_bytes = code.size() * sizeof(u64);
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auto registry = std::make_shared<Registry>(shader_type, params.system.GPU().Maxwell3D());
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const ShaderIR ir(code, STAGE_MAIN_OFFSET, COMPILER_SETTINGS, *registry);
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const ShaderIR ir(code, shader_type, STAGE_MAIN_OFFSET, COMPILER_SETTINGS, *registry);
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// TODO(Rodrigo): Handle VertexA shaders
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// std::optional<ShaderIR> ir_b;
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// if (!code_b.empty()) {
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@ -264,7 +264,7 @@ Shader CachedShader::CreateKernelFromMemory(const ShaderParameters& params, Prog
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auto& engine = params.system.GPU().KeplerCompute();
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auto registry = std::make_shared<Registry>(ShaderType::Compute, engine);
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const ShaderIR ir(code, KERNEL_MAIN_OFFSET, COMPILER_SETTINGS, *registry);
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const ShaderIR ir(code, ShaderType::Compute, KERNEL_MAIN_OFFSET, COMPILER_SETTINGS, *registry);
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const u64 uid = params.unique_identifier;
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auto program = BuildShader(params.device, ShaderType::Compute, uid, ir, *registry);
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@ -341,7 +341,7 @@ void ShaderCacheOpenGL::LoadDiskCache(const std::atomic_bool& stop_loading,
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const bool is_compute = entry.type == ShaderType::Compute;
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const u32 main_offset = is_compute ? KERNEL_MAIN_OFFSET : STAGE_MAIN_OFFSET;
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auto registry = MakeRegistry(entry);
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const ShaderIR ir(entry.code, main_offset, COMPILER_SETTINGS, *registry);
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const ShaderIR ir(entry.code, entry.type, main_offset, COMPILER_SETTINGS, *registry);
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std::shared_ptr<OGLProgram> program;
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if (precompiled_entry) {
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@ -162,7 +162,8 @@ CachedShader::CachedShader(Core::System& system, Tegra::Engines::ShaderType stag
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ProgramCode program_code, u32 main_offset)
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: RasterizerCacheObject{host_ptr}, gpu_addr{gpu_addr}, cpu_addr{cpu_addr},
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program_code{std::move(program_code)}, registry{stage, GetEngine(system, stage)},
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shader_ir{this->program_code, main_offset, compiler_settings, registry},
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shader_ir{this->program_code, stage, main_offset, compiler_settings,
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registry},
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entries{GenerateShaderEntries(shader_ir)} {}
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CachedShader::~CachedShader() = default;
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@ -24,9 +24,10 @@ using Tegra::Shader::PredCondition;
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using Tegra::Shader::PredOperation;
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using Tegra::Shader::Register;
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ShaderIR::ShaderIR(const ProgramCode& program_code, u32 main_offset, CompilerSettings settings,
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Registry& registry)
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: program_code{program_code}, main_offset{main_offset}, settings{settings}, registry{registry} {
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ShaderIR::ShaderIR(const ProgramCode& program_code, Tegra::Engines::ShaderType shader_stage,
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u32 main_offset, CompilerSettings settings, Registry& registry)
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: program_code{program_code}, shader_stage{shader_stage},
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main_offset{main_offset}, settings{settings}, registry{registry} {
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Decode();
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PostDecode();
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}
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@ -68,8 +68,8 @@ struct GlobalMemoryUsage {
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class ShaderIR final {
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public:
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explicit ShaderIR(const ProgramCode& program_code, u32 main_offset, CompilerSettings settings,
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Registry& registry);
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explicit ShaderIR(const ProgramCode& program_code, Tegra::Engines::ShaderType shader_stage,
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u32 main_offset, CompilerSettings settings, Registry& registry);
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~ShaderIR();
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const std::map<u32, NodeBlock>& GetBasicBlocks() const {
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@ -419,6 +419,7 @@ private:
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u32 NewCustomVariable();
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const ProgramCode& program_code;
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const Tegra::Engines::ShaderType shader_stage;
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const u32 main_offset;
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const CompilerSettings settings;
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Registry& registry;
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