forked from ShuriZma/suyu
shader/arithmetic: Implement FCMP immediate + register variant
Trivially add the encoding for this.
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725fcbb368
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@ -1893,6 +1893,7 @@ public:
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ICMP_IMM,
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ICMP_IMM,
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FCMP_RR,
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FCMP_RR,
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FCMP_RC,
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FCMP_RC,
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FCMP_IMMR,
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MUFU, // Multi-Function Operator
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MUFU, // Multi-Function Operator
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RRO_C, // Range Reduction Operator
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RRO_C, // Range Reduction Operator
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RRO_R,
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RRO_R,
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@ -2205,6 +2206,7 @@ private:
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INST("0111110-0-------", Id::HSET2_IMM, Type::HalfSet, "HSET2_IMM"),
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INST("0111110-0-------", Id::HSET2_IMM, Type::HalfSet, "HSET2_IMM"),
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INST("010110111010----", Id::FCMP_RR, Type::Arithmetic, "FCMP_RR"),
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INST("010110111010----", Id::FCMP_RR, Type::Arithmetic, "FCMP_RR"),
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INST("010010111010----", Id::FCMP_RC, Type::Arithmetic, "FCMP_RC"),
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INST("010010111010----", Id::FCMP_RC, Type::Arithmetic, "FCMP_RC"),
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INST("0011011-1010----", Id::FCMP_IMMR, Type::Arithmetic, "FCMP_IMMR"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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@ -137,7 +137,8 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
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break;
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break;
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}
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}
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case OpCode::Id::FCMP_RR:
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case OpCode::Id::FCMP_RR:
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case OpCode::Id::FCMP_RC: {
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case OpCode::Id::FCMP_RC:
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case OpCode::Id::FCMP_IMMR: {
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UNIMPLEMENTED_IF(instr.fcmp.ftz == 0);
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UNIMPLEMENTED_IF(instr.fcmp.ftz == 0);
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Node op_c = GetRegister(instr.gpr39);
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Node op_c = GetRegister(instr.gpr39);
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Node comp = GetPredicateComparisonFloat(instr.fcmp.cond, std::move(op_c), Immediate(0.0f));
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Node comp = GetPredicateComparisonFloat(instr.fcmp.cond, std::move(op_c), Immediate(0.0f));
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