forked from ShuriZma/suyu
GPU: Delay Fences.
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8b1eb44b3e
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@ -34,6 +34,7 @@ void DmaPusher::DispatchCalls() {
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}
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}
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gpu.FlushCommands();
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gpu.FlushCommands();
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gpu.SyncGuestHost();
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gpu.SyncGuestHost();
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gpu.OnCommandListEnd();
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}
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}
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bool DmaPusher::Step() {
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bool DmaPusher::Step() {
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@ -397,6 +397,14 @@ void Maxwell3D::StampQueryResult(u64 payload, bool long_query) {
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}
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}
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}
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}
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void Maxwell3D::ReleaseFences() {
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for (const auto pair : delay_fences) {
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const auto [addr, payload] = pair;
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memory_manager.Write<u32>(addr, static_cast<u32>(payload));
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}
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delay_fences.clear();
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}
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void Maxwell3D::ProcessQueryGet() {
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void Maxwell3D::ProcessQueryGet() {
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// TODO(Subv): Support the other query units.
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// TODO(Subv): Support the other query units.
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ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
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ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
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@ -407,7 +415,7 @@ void Maxwell3D::ProcessQueryGet() {
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rasterizer.FlushCommands();
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rasterizer.FlushCommands();
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rasterizer.SyncGuestHost();
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rasterizer.SyncGuestHost();
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const u64 result = regs.query.query_sequence;
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const u64 result = regs.query.query_sequence;
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StampQueryResult(result, regs.query.query_get.short_query == 0);
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delay_fences.emplace_back(regs.query.QueryAddress(), result);
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break;
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break;
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}
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}
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case Regs::QueryOperation::Acquire:
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case Regs::QueryOperation::Acquire:
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@ -1427,6 +1427,8 @@ public:
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Tables tables{};
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Tables tables{};
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} dirty;
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} dirty;
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void ReleaseFences();
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private:
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private:
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void InitializeRegisterDefaults();
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void InitializeRegisterDefaults();
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@ -1467,6 +1469,8 @@ private:
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std::array<u8, Regs::NUM_REGS> dirty_pointers{};
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std::array<u8, Regs::NUM_REGS> dirty_pointers{};
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std::vector<std::pair<GPUVAddr, u64>> delay_fences;
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/// Retrieves information about a specific TIC entry from the TIC buffer.
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/// Retrieves information about a specific TIC entry from the TIC buffer.
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Texture::TICEntry GetTICEntry(u32 tic_index) const;
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Texture::TICEntry GetTICEntry(u32 tic_index) const;
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@ -145,6 +145,10 @@ void GPU::FlushCommands() {
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void GPU::SyncGuestHost() {
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void GPU::SyncGuestHost() {
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renderer->Rasterizer().SyncGuestHost();
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renderer->Rasterizer().SyncGuestHost();
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}
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}
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void GPU::OnCommandListEnd() {
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maxwell_3d->ReleaseFences();
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}
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// Note that, traditionally, methods are treated as 4-byte addressable locations, and hence
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// Note that, traditionally, methods are treated as 4-byte addressable locations, and hence
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// their numbers are written down multiplied by 4 in Docs. Here we are not multiply by 4.
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// their numbers are written down multiplied by 4 in Docs. Here we are not multiply by 4.
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// So the values you see in docs might be multiplied by 4.
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// So the values you see in docs might be multiplied by 4.
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@ -157,6 +157,7 @@ public:
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void FlushCommands();
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void FlushCommands();
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void SyncGuestHost();
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void SyncGuestHost();
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void OnCommandListEnd();
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/// Returns a reference to the Maxwell3D GPU engine.
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/// Returns a reference to the Maxwell3D GPU engine.
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Engines::Maxwell3D& Maxwell3D();
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Engines::Maxwell3D& Maxwell3D();
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@ -78,7 +78,7 @@ void ThreadManager::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
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}
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}
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void ThreadManager::FlushRegion(VAddr addr, u64 size) {
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void ThreadManager::FlushRegion(VAddr addr, u64 size) {
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system.Renderer().Rasterizer().FlushRegion(addr, size);
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PushCommand(FlushRegionCommand(addr, size));
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}
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}
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void ThreadManager::InvalidateRegion(VAddr addr, u64 size) {
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void ThreadManager::InvalidateRegion(VAddr addr, u64 size) {
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