forked from ShuriZma/suyu
Enable depth test on stencil clear path
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parent
df56ecc318
commit
1a246bf135
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@ -609,6 +609,8 @@ void BlitImageHelper::ClearDepthStencil(const Framebuffer* dst_framebuffer, bool
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const VkPipelineLayout layout = *clear_color_pipeline_layout;
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scheduler.RequestRenderpass(dst_framebuffer);
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scheduler.Record([pipeline, layout, clear_depth, dst_region](vk::CommandBuffer cmdbuf) {
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constexpr std::array blend_constants{0.0f, 0.0f, 0.0f, 0.0f};
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cmdbuf.SetBlendConstants(blend_constants.data());
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cmdbuf.BindPipeline(VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
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BindBlitState(cmdbuf, dst_region);
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cmdbuf.PushConstants(layout, VK_SHADER_STAGE_FRAGMENT_BIT, clear_depth);
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@ -865,7 +867,7 @@ VkPipeline BlitImageHelper::FindOrEmplaceClearStencilPipeline(
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.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
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.pNext = nullptr,
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.flags = 0,
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.depthTestEnable = VK_FALSE,
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.depthTestEnable = key.depth_clear,
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.depthWriteEnable = key.depth_clear,
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.depthCompareOp = VK_COMPARE_OP_ALWAYS,
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.depthBoundsTestEnable = VK_FALSE,
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@ -429,7 +429,8 @@ void RasterizerVulkan::Clear(u32 layer_count) {
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return;
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}
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if (use_stencil && regs.stencil_front_mask != 0xFF && regs.stencil_front_mask != 0) {
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if (use_stencil && framebuffer->HasAspectStencilBit() && regs.stencil_front_mask != 0xFF &&
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regs.stencil_front_mask != 0) {
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Region2D dst_region = {
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Offset2D{.x = clear_rect.rect.offset.x, .y = clear_rect.rect.offset.y},
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Offset2D{.x = clear_rect.rect.offset.x + static_cast<s32>(clear_rect.rect.extent.width),
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