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shader: Add FP64 register load/store helpers

This commit is contained in:
ameerj 2021-03-21 01:32:02 -04:00
parent a77e764726
commit 112b8f00f0
3 changed files with 24 additions and 21 deletions
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16
src/shader_recompiler/frontend/maxwell/translate/impl/double_add.cpp
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@ -22,19 +22,11 @@ void DADD(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
BitField<48, 1, u64> neg_a; BitField<48, 1, u64> neg_a;
BitField<49, 1, u64> abs_b; BitField<49, 1, u64> abs_b;
} const dadd{insn}; } const dadd{insn};
if (!IR::IsAligned(dadd.dest_reg, 2)) {
throw NotImplementedException("Unaligned destination register {}", dadd.dest_reg.Value());
}
if (!IR::IsAligned(dadd.src_a_reg, 2)) {
throw NotImplementedException("Unaligned destination register {}", dadd.src_a_reg.Value());
}
if (dadd.cc != 0) { if (dadd.cc != 0) {
throw NotImplementedException("DADD CC"); throw NotImplementedException("DADD CC");
} }
const IR::Reg reg_a{dadd.src_a_reg}; const IR::F64 src_a{v.D(dadd.src_a_reg)};
const IR::F64 src_a{v.ir.PackDouble2x32(v.ir.CompositeConstruct(v.X(reg_a), v.X(reg_a + 1)))};
const IR::F64 op_a{v.ir.FPAbsNeg(src_a, dadd.abs_a != 0, dadd.neg_a != 0)}; const IR::F64 op_a{v.ir.FPAbsNeg(src_a, dadd.abs_a != 0, dadd.neg_a != 0)};
const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dadd.abs_b != 0, dadd.neg_b != 0)}; const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dadd.abs_b != 0, dadd.neg_b != 0)};
@ -43,12 +35,8 @@ void DADD(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
.rounding{CastFpRounding(dadd.fp_rounding)}, .rounding{CastFpRounding(dadd.fp_rounding)},
.fmz_mode{IR::FmzMode::None}, .fmz_mode{IR::FmzMode::None},
}; };
const IR::F64 value{v.ir.FPAdd(op_a, op_b, control)};
const IR::Value result{v.ir.UnpackDouble2x32(value)};
for (int i = 0; i < 2; i++) { v.D(dadd.dest_reg, v.ir.FPAdd(op_a, op_b, control));
v.X(dadd.dest_reg + i, IR::U32{v.ir.CompositeExtract(result, i)});
}
} }
} // Anonymous namespace } // Anonymous namespace

27
src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
View File

@ -25,6 +25,13 @@ IR::F32 TranslatorVisitor::F(IR::Reg reg) {
return ir.BitCast<IR::F32>(X(reg)); return ir.BitCast<IR::F32>(X(reg));
} }
IR::F64 TranslatorVisitor::D(IR::Reg reg) {
if (!IR::IsAligned(reg, 2)) {
throw NotImplementedException("Unaligned source register {}", reg);
}
return IR::F64{ir.PackDouble2x32(ir.CompositeConstruct(X(reg), X(reg + 1)))};
}
void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) { void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) {
ir.SetReg(dest_reg, value); ir.SetReg(dest_reg, value);
} }
@ -33,6 +40,16 @@ void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) {
X(dest_reg, ir.BitCast<IR::U32>(value)); X(dest_reg, ir.BitCast<IR::U32>(value));
} }
void TranslatorVisitor::D(IR::Reg dest_reg, const IR::F64& value) {
if (!IR::IsAligned(dest_reg, 2)) {
throw NotImplementedException("Unaligned destination register {}", dest_reg);
}
const IR::Value result{ir.UnpackDouble2x32(value)};
for (int i = 0; i < 2; i++) {
X(dest_reg + i, IR::U32{ir.CompositeExtract(result, i)});
}
}
IR::U32 TranslatorVisitor::GetReg8(u64 insn) { IR::U32 TranslatorVisitor::GetReg8(u64 insn) {
union { union {
u64 raw; u64 raw;
@ -68,13 +85,9 @@ IR::F32 TranslatorVisitor::GetFloatReg39(u64 insn) {
IR::F64 TranslatorVisitor::GetDoubleReg20(u64 insn) { IR::F64 TranslatorVisitor::GetDoubleReg20(u64 insn) {
union { union {
u64 raw; u64 raw;
BitField<20, 8, IR::Reg> src; BitField<20, 8, IR::Reg> index;
} const index{insn}; } const reg{insn};
const IR::Reg reg{index.src}; return D(reg.index);
if (!IR::IsAligned(reg, 2)) {
throw NotImplementedException("Unaligned source register {}", reg);
}
return ir.PackDouble2x32(ir.CompositeConstruct(X(reg), X(reg + 1)));
} }
static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) { static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) {

2
src/shader_recompiler/frontend/maxwell/translate/impl/impl.h
View File

@ -342,9 +342,11 @@ public:
[[nodiscard]] IR::U32 X(IR::Reg reg); [[nodiscard]] IR::U32 X(IR::Reg reg);
[[nodiscard]] IR::F32 F(IR::Reg reg); [[nodiscard]] IR::F32 F(IR::Reg reg);
[[nodiscard]] IR::F64 D(IR::Reg reg);
void X(IR::Reg dest_reg, const IR::U32& value); void X(IR::Reg dest_reg, const IR::U32& value);
void F(IR::Reg dest_reg, const IR::F32& value); void F(IR::Reg dest_reg, const IR::F32& value);
void D(IR::Reg dest_reg, const IR::F64& value);
[[nodiscard]] IR::U32 GetReg8(u64 insn); [[nodiscard]] IR::U32 GetReg8(u64 insn);
[[nodiscard]] IR::U32 GetReg20(u64 insn); [[nodiscard]] IR::U32 GetReg20(u64 insn);