Peter Maydell 8e18cde30b target-arm: Fix VLD of single element to all lanes ... Fix several bugs in VLD of single element to all lanes: The "single element to all lanes" form of VLD1 differs from those for VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element should be written to one or two Dregs (rather than being a register stride). Handle this by special-casing VLD1 rather than trying to have one loop which deals with both VLD1 and 2/3/4. Handle VLD4.32 with 16 byte alignment specified, rather than UNDEFfing. UNDEF for the invalid size and alignment combinations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2011-04-01 22:33:47 +02:00
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cpu.h	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
exec.h	inline cpu_halted into sole caller	2011-03-13 14:44:21 +00:00
helper.c	target-arm: use make_float32() to make constant floats for VRSQRTS	2011-03-22 07:59:07 +01:00
helpers.h	target-arm: Move Neon VZIP to helper functions	2011-02-20 17:31:53 +01:00
iwmmxt_helper.c	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
machine.c	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
neon_helper.c	target-arm: Fix unsigned VQRSHL by large shift counts	2011-02-20 17:43:01 +01:00
op_addsub.h	target-arm: fix addsub/subadd implementation	2010-07-01 23:45:29 +02:00
op_helper.c	Set the right overflow bit for neon 32 and 64 bit saturating add/sub.	2011-02-04 20:57:41 +01:00
translate.c	target-arm: Fix VLD of single element to all lanes	2011-04-01 22:33:47 +02:00