xqemu

Commit Graph

Author	SHA1	Message	Date
Anthony Liguori	999e12bbe8	sysbus: apic: ioapic: convert to QEMU Object Model This converts three devices because apic and ioapic are subclasses of sysbus. Converting subclasses independently of their base class is prohibitively hard. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>	2012-01-27 10:50:50 -06:00
Rob Herring	b2123a4856	add L2x0/PL310 cache controller device This is just a dummy device for ARM L2 cache controllers, based on the pl310. The cache type parameter can be defined by a property value and has a meaningful default. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> [Peter Maydell: removed stray blank line at end] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>	2012-01-04 13:41:42 +00:00

Author

SHA1

Message

Date

Anthony Liguori

999e12bbe8

sysbus: apic: ioapic: convert to QEMU Object Model

This converts three devices because apic and ioapic are subclasses of sysbus.
Converting subclasses independently of their base class is prohibitively hard.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>

2012-01-27 10:50:50 -06:00

Rob Herring

b2123a4856

add L2x0/PL310 cache controller device

This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
[Peter Maydell: removed stray blank line at end]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2012-01-04 13:41:42 +00:00

2 Commits