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144 Commits

Author SHA1 Message Date
aurel32 489251fa54 ppc: replace op_set_FT0 with tcg_gen_movi_i64 
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5162 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 20:34:31 +00:00
aurel32 bd568f1849 ppc: Convert nip moves to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5160 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 18:06:03 +00:00
aurel32 d38ff48941 ppc: remove unused code 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5159 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 17:16:41 +00:00
aurel32 47e4661cc4 ppc: Convert CRF moves to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 17:06:47 +00:00
aurel32 ec1ac72d9c ppc: fix fpr TCG registers creation 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5157 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 15:49:12 +00:00
aurel32 a5e26afa61 ppc: Convert FPR moves to TCG 
Replace op_{load,store}_fpr with tcg_gen_mov_i64.
Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2].

This obsoletes op_template.h for REG > 7.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5156 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 14:43:54 +00:00
aurel32 1d54269590 ppc: Convert Altivec register moves to TCG 
Replace op_{load,store}_avr with helpers gen_{load,store}_avr.
Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and
cpu_AVR{h,l}[0..2].

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5155 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 14:43:45 +00:00
aurel32 bd7d9a6d7b ppc: cleanup register types 
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 05:26:09 +00:00
aurel32 f78fb44e82 ppc: Convert GPR moves to TCG 
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 05:25:47 +00:00
aurel32 f0413473ff [ppc] Convert op_moven_T2_T0 to TCG 
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5143 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 23:26:40 +00:00
aurel32 86c581dc80 [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG 
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5142 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 23:26:32 +00:00
aurel32 e55fd9340e [ppc] Convert op_move_{T1,T2}_T0 to TCG 
Attached patch replaces op_move_T1_T0 and op_move_T2_T0 with
tcg_gen_mov_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5137 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 16:19:05 +00:00
aurel32 02f4f6c24c [ppc] Convert gen_set_{T0,T1} to TCG 
The attached patch replaces gen_set_T0 and gen_set_T1 with
tcg_gen_movi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5136 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 16:18:55 +00:00
aurel32 f10dc08e00 PPC: add support for TCG helpers 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5094 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:01:45 +00:00
aurel32 1c73fe5bba PPC: Init TCG variables 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5093 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:01:36 +00:00
aurel32 6676f42453 Revert commits 5082 and 5083 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5084 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-24 23:16:35 +00:00
aurel32 61c0480722 PPC: Switch a few instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5083 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-24 19:05:35 +00:00
aurel32 c0692e3c65 PPC: Init TCG variables 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5082 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-24 19:05:26 +00:00
ths 9ceb2a77ad Fix encoding of efsctsiz (powerpc spe), by Tristan Gingold. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4999 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-13 11:30:10 +00:00
ths 2cfc5f17d3 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-18 18:01:29 +00:00
pbrook b2437bf267 Add missing static qualifiers. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 12:29:56 +00:00
pbrook 2e70f6efa8 Add instruction counter. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 01:03:05 +00:00
aurel32 e4bb997e06 PPC: fix mtfsfi 
(Tristan Gingold)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4748 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-18 22:10:12 +00:00
ths 1235fc066a Spelling fixes, by Stefan Weil. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4655 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-03 19:51:57 +00:00
aurel32 8cbcb4fa2c Fix broken PPC user space single stepping 
(Jason Wessel)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4421 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 23:28:14 +00:00
aurel32 fd501a05c6 PPC: fix isel opcode decoding 
(Tristan Gingold)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4345 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-05 21:27:18 +00:00
aurel32 d2856f1ad4 Factorize code in translate.c 
(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-28 00:32:32 +00:00
aurel32 ca10f86763 Remove osdep.c/qemu-img code duplication 
(Kevin Wolf)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-11 21:35:42 +00:00
bellard 57fec1fee9 use the TCG code generator 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-01 10:50:11 +00:00
j_mayer 6b542af760 Fix incorrect debug prints (reported by Paul Brook). 
Remove obsolete / duplicated debug prints and improve output consistency.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-24 02:03:55 +00:00
j_mayer e7c240035f Add new sane low-level memory accessors for PowerPC that do proper 
size or zero extension, with homogenous names.
Fix load & store strings: those are now endian-sensitive, by definition.
Fix dcbz: must always align the target address to a cache line boundary.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3719 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-22 11:00:46 +00:00
j_mayer 5b8105fa50 PowerPC instruction fixes: 
- hrfid is part of the hypervisor extension
- fix stfiwx naming


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3705 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-19 11:39:29 +00:00
j_mayer c8623f2e37 Fix another collision in PowerPC instructions definitions. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3702 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-19 01:48:51 +00:00
j_mayer 05332d70fd A little more granularity in PowerPC instructions definition is needed 
in order to implement Freescale cores.
Fix efsadd / efssub opcodes.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3679 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-17 22:26:51 +00:00
j_mayer f610349f36 Fix collision in PowerPC instructions definitions. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3668 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-17 12:01:45 +00:00
j_mayer 7863667f35 Always make PowerPC hypervisor mode memory accesses and instructions 
available for full system emulation, then removing all #if TARGET_PPC64H
  from micro-ops and code translator.
Add new macros to dramatically simplify memory access tables definitions
  in target-ppc/translate.c.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3654 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-16 14:11:28 +00:00
j_mayer 271a916e8a Fix invalid PowerPC 64 rldimi optimized case. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3638 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-14 05:26:46 +00:00
j_mayer 1b413d5563 Reorganize PowerPC instructions categories, add icbi separate case. 
Fix frsqrtes instruction opcode.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3636 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-14 01:08:45 +00:00
j_mayer 65d6c0f33c PowerPC SPE extension fix: must always preserve GPR high bits when 
running in 32 bits mode.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-12 23:29:14 +00:00
j_mayer 3cd7d1ddbb Allow use of SPE extension by all PowerPC targets, 
adding gprh registers to store GPR MSBs when GPRs are 32 bits.
Remove not-needed-anymore ppcemb-linux-user target.
Keep ppcemb-softmmu target, which provides 1kB pages support
  and 36 bits physical address space.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3628 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-12 01:56:18 +00:00
j_mayer 6f2d897872 Fix usage of the -1 constant in the PowerPC target code: 
fix invalid size casts and/or sign-extensions.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3626 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-12 00:04:48 +00:00
j_mayer c3e10c7b43 Optimize PowerPC overflow flag computation in most useful cases. 
Use the same routines to check overflow for addo, subfo and PowerPC 405
  multiply and add cases.
Fix carry reset in addme(o) and subfme(o) cases.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3574 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-11 00:18:34 +00:00
j_mayer 056401eae6 PowerPC 601 need specific callbacks for its BATs setup. 
Implement PowerPC 601 HID0 register, needed for little-endian mode support.
As a consequence, we need to merge hflags coming from MSR with other ones.
Use little-endian mode from hflags instead of MSR during code translation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3524 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-04 02:55:33 +00:00
j_mayer 077fc2061e Improve PowerPC CPU state dump. 
Dump NIP on SPR access faults.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3522 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-04 01:57:29 +00:00
j_mayer 9fceefa7d1 Don't print any message when a priviledge exception occurs on mfpvr 
as the Linux allows applications to read this register.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3510 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-02 22:47:50 +00:00
j_mayer fc0d441e14 Fix CR ops with complement, thanks to Julian Seward for testing 
and reporting the bug :
* remove bugged CR ops specific micro-ops
* use standard and / or / shift operations instead
* comment not-used-anymore op_store_T1_crf_crf micro-op template.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3501 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-31 22:02:17 +00:00
j_mayer a11b8151df PowerPC coding style and inlining fixes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3461 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-28 00:55:05 +00:00
j_mayer 7c58044c0a Fix PowerPC FPSCR update and floating-point exception generation 
in most useful cases.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3458 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-27 17:54:30 +00:00
j_mayer dac454af57 Bugfix in PowerPC dcbi instruction: 
we must do a load before the store, or we'll store random data.
Update cache instructions comments.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3448 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-26 00:48:00 +00:00
j_mayer c7697e1f51 Pretty dump for specific PowerPC instructions names. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3447 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-26 00:46:07 +00:00