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5 Commits

Author SHA1 Message Date
Richard Henderson 9940a96bc8 tcg: Allow target-specific implementation of NAND. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:44:40 +01:00
Richard Henderson 8d625cf1d1 tcg: Allow target-specific implementation of EQV. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:42:46 +01:00
Paolo Bonzini a63b5829af remove remaining occurrences AREG[1-9] and TCG_AREG[1-9] 
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 20:48:30 +01:00
Richard Henderson 3682825669 tcg: Add comments for all optional instructions not implemented. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2010-02-20 08:35:12 +00:00
Aurelien Jarno afa05235a5 tcg: initial mips support 
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>

A few words about design choices:
* Two registers, at and t0, are reserved for TCG internal use. They are
  useful for bswap and 64-bit ops.
* Most ops supports a constant argument with value 0, which is actually
  mapped to the zero register.
* While the at register is available for constant loading, ops only
  support a limited range of constants. TCG does a better job doing the
  register allocation and constant loading by itself. There are plenty of
  registers available anyway.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-12-01 00:06:15 +00:00