mirror of https://github.com/xqemu/xqemu.git
Convert float move ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4090 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
75b680e523
commit
ff07ec8309
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@ -1,128 +0,0 @@
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/*
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* SPARC micro operations (templates for various register related
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* operations)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* floating point registers moves */
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void OPPROTO glue(op_load_fpr_FT0_fpr, REGNAME)(void)
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{
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FT0 = REG;
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}
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void OPPROTO glue(op_store_FT0_fpr_fpr, REGNAME)(void)
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{
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REG = FT0;
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}
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void OPPROTO glue(op_load_fpr_FT1_fpr, REGNAME)(void)
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{
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FT1 = REG;
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}
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void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void)
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{
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REG = FT1;
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}
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/* double floating point registers moves */
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void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void)
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{
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CPU_DoubleU u;
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uint32_t *p = (uint32_t *)®
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u.l.lower = *(p +1);
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u.l.upper = *p;
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DT0 = u.d;
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}
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void OPPROTO glue(op_store_DT0_fpr_fpr, REGNAME)(void)
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{
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CPU_DoubleU u;
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uint32_t *p = (uint32_t *)®
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u.d = DT0;
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*(p +1) = u.l.lower;
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*p = u.l.upper;
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}
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void OPPROTO glue(op_load_fpr_DT1_fpr, REGNAME)(void)
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{
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CPU_DoubleU u;
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uint32_t *p = (uint32_t *)®
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u.l.lower = *(p +1);
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u.l.upper = *p;
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DT1 = u.d;
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}
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void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void)
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{
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CPU_DoubleU u;
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uint32_t *p = (uint32_t *)®
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u.d = DT1;
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*(p +1) = u.l.lower;
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*p = u.l.upper;
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}
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#if defined(CONFIG_USER_ONLY)
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/* quad floating point registers moves */
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void OPPROTO glue(op_load_fpr_QT0_fpr, REGNAME)(void)
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{
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CPU_QuadU u;
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uint32_t *p = (uint32_t *)®
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u.l.lowest = *(p + 3);
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u.l.lower = *(p + 2);
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u.l.upper = *(p + 1);
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u.l.upmost = *p;
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QT0 = u.q;
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}
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void OPPROTO glue(op_store_QT0_fpr_fpr, REGNAME)(void)
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{
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CPU_QuadU u;
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uint32_t *p = (uint32_t *)®
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u.q = QT0;
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*(p + 3) = u.l.lowest;
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*(p + 2) = u.l.lower;
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*(p + 1) = u.l.upper;
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*p = u.l.upmost;
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}
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void OPPROTO glue(op_load_fpr_QT1_fpr, REGNAME)(void)
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{
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CPU_QuadU u;
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uint32_t *p = (uint32_t *)®
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u.l.lowest = *(p + 3);
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u.l.lower = *(p + 2);
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u.l.upper = *(p + 1);
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u.l.upmost = *p;
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QT1 = u.q;
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}
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void OPPROTO glue(op_store_QT1_fpr_fpr, REGNAME)(void)
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{
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CPU_QuadU u;
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uint32_t *p = (uint32_t *)®
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u.q = QT1;
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*(p + 3) = u.l.lowest;
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*(p + 2) = u.l.lower;
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*(p + 1) = u.l.upper;
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*p = u.l.upmost;
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}
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#endif
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#undef REG
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#undef REGNAME
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@ -21,154 +21,6 @@
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#include "exec.h"
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#include "helper.h"
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#define REGNAME f0
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#define REG (env->fpr[0])
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#include "fop_template.h"
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#define REGNAME f1
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#define REG (env->fpr[1])
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#include "fop_template.h"
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#define REGNAME f2
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#define REG (env->fpr[2])
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#include "fop_template.h"
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#define REGNAME f3
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#define REG (env->fpr[3])
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#include "fop_template.h"
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#define REGNAME f4
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#define REG (env->fpr[4])
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#include "fop_template.h"
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#define REGNAME f5
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#define REG (env->fpr[5])
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#include "fop_template.h"
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#define REGNAME f6
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#define REG (env->fpr[6])
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#include "fop_template.h"
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#define REGNAME f7
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#define REG (env->fpr[7])
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#include "fop_template.h"
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#define REGNAME f8
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#define REG (env->fpr[8])
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#include "fop_template.h"
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#define REGNAME f9
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#define REG (env->fpr[9])
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#include "fop_template.h"
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#define REGNAME f10
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#define REG (env->fpr[10])
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#include "fop_template.h"
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#define REGNAME f11
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#define REG (env->fpr[11])
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#include "fop_template.h"
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#define REGNAME f12
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#define REG (env->fpr[12])
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#include "fop_template.h"
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#define REGNAME f13
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#define REG (env->fpr[13])
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#include "fop_template.h"
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#define REGNAME f14
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#define REG (env->fpr[14])
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#include "fop_template.h"
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#define REGNAME f15
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#define REG (env->fpr[15])
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#include "fop_template.h"
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#define REGNAME f16
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#define REG (env->fpr[16])
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#include "fop_template.h"
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#define REGNAME f17
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#define REG (env->fpr[17])
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#include "fop_template.h"
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#define REGNAME f18
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#define REG (env->fpr[18])
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#include "fop_template.h"
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#define REGNAME f19
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#define REG (env->fpr[19])
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#include "fop_template.h"
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#define REGNAME f20
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#define REG (env->fpr[20])
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#include "fop_template.h"
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#define REGNAME f21
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#define REG (env->fpr[21])
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#include "fop_template.h"
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#define REGNAME f22
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#define REG (env->fpr[22])
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#include "fop_template.h"
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#define REGNAME f23
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#define REG (env->fpr[23])
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#include "fop_template.h"
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#define REGNAME f24
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#define REG (env->fpr[24])
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#include "fop_template.h"
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#define REGNAME f25
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#define REG (env->fpr[25])
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#include "fop_template.h"
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#define REGNAME f26
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#define REG (env->fpr[26])
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#include "fop_template.h"
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#define REGNAME f27
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#define REG (env->fpr[27])
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#include "fop_template.h"
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#define REGNAME f28
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#define REG (env->fpr[28])
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#include "fop_template.h"
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#define REGNAME f29
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#define REG (env->fpr[29])
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#include "fop_template.h"
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#define REGNAME f30
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#define REG (env->fpr[30])
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#include "fop_template.h"
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#define REGNAME f31
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#define REG (env->fpr[31])
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#include "fop_template.h"
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#ifdef TARGET_SPARC64
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#define REGNAME f32
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#define REG (env->fpr[32])
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#include "fop_template.h"
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#define REGNAME f34
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#define REG (env->fpr[34])
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#include "fop_template.h"
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#define REGNAME f36
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#define REG (env->fpr[36])
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#include "fop_template.h"
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#define REGNAME f38
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#define REG (env->fpr[38])
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#include "fop_template.h"
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#define REGNAME f40
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#define REG (env->fpr[40])
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#include "fop_template.h"
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#define REGNAME f42
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#define REG (env->fpr[42])
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#include "fop_template.h"
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#define REGNAME f44
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#define REG (env->fpr[44])
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#include "fop_template.h"
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#define REGNAME f46
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#define REG (env->fpr[46])
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#include "fop_template.h"
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#define REGNAME f48
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#define REG (env->fpr[47])
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#include "fop_template.h"
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#define REGNAME f50
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#define REG (env->fpr[50])
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#include "fop_template.h"
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#define REGNAME f52
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#define REG (env->fpr[52])
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#include "fop_template.h"
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#define REGNAME f54
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#define REG (env->fpr[54])
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#include "fop_template.h"
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#define REGNAME f56
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#define REG (env->fpr[56])
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#include "fop_template.h"
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#define REGNAME f58
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#define REG (env->fpr[58])
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#include "fop_template.h"
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#define REGNAME f60
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#define REG (env->fpr[60])
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#include "fop_template.h"
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#define REGNAME f62
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#define REG (env->fpr[62])
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#include "fop_template.h"
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#endif
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/* Load and store */
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#define MEMSUFFIX _raw
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#include "op_mem.h"
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@ -114,60 +114,85 @@ static int sign_extend(int x, int len)
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static void disas_sparc_insn(DisasContext * dc);
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#ifdef TARGET_SPARC64
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#define GEN32(func, NAME) \
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static GenOpFunc * const NAME ## _table [64] = { \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
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NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
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NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
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NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
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NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
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}; \
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static inline void func(int n) \
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{ \
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NAME ## _table[n](); \
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}
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#else
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#define GEN32(func, NAME) \
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static GenOpFunc *const NAME ## _table [32] = { \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
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}; \
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static inline void func(int n) \
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{ \
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NAME ## _table[n](); \
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}
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#endif
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/* floating point registers moves */
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GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
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GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
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GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
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GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
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static void gen_op_load_fpr_FT0(unsigned int src)
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{
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
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}
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GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
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GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
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GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
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GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
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static void gen_op_load_fpr_FT1(unsigned int src)
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{
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft1));
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}
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#if defined(CONFIG_USER_ONLY)
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GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
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GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
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GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
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GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
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static void gen_op_store_FT0_fpr(unsigned int dst)
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{
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, ft0));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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}
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static void gen_op_load_fpr_DT0(unsigned int src)
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{
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
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}
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static void gen_op_load_fpr_DT1(unsigned int src)
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{
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
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}
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static void gen_op_store_DT0_fpr(unsigned int dst)
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{
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
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}
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#ifdef CONFIG_USER_ONLY
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static void gen_op_load_fpr_QT0(unsigned int src)
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{
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
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}
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static void gen_op_load_fpr_QT1(unsigned int src)
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{
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tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src]));
|
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tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
|
||||
tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
|
||||
tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
|
||||
tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
|
||||
tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
|
||||
tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
|
||||
tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
|
||||
}
|
||||
|
||||
static void gen_op_store_QT0_fpr(unsigned int dst)
|
||||
{
|
||||
tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
|
||||
tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
|
||||
tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
|
||||
tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
|
||||
tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
|
||||
tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
|
||||
tcg_gen_ld_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
|
||||
tcg_gen_st_i32(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
|
||||
}
|
||||
#endif
|
||||
|
||||
/* moves */
|
||||
|
|
|
|||
Loading…
Reference in New Issue