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target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA 

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Bastian Koppelmann 2015-05-06 20:22:45 +02:00
parent 6d2afc8a5e
commit fcecf12684
1 changed files with 9 additions and 2 deletions
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11
target-tricore/translate.c
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@ -3485,7 +3485,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
* Functions for decoding instructions * Functions for decoding instructions
*/ */
static void decode_src_opc(DisasContext *ctx, int op1) static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
{ {
int r1; int r1;
int32_t const4; int32_t const4;
@ -3546,6 +3546,12 @@ static void decode_src_opc(DisasContext *ctx, int op1)
const4 = MASK_OP_SRC_CONST4(ctx->opcode); const4 = MASK_OP_SRC_CONST4(ctx->opcode);
tcg_gen_movi_tl(cpu_gpr_a[r1], const4); tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
break; break;
case OPC1_16_SRC_MOV_E:
if (tricore_feature(env, TRICORE_FEATURE_16)) {
tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
} /* TODO: else raise illegal opcode trap */
break;
case OPC1_16_SRC_SH: case OPC1_16_SRC_SH:
gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
break; break;
@ -3883,9 +3889,10 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
case OPC1_16_SRC_LT: case OPC1_16_SRC_LT:
case OPC1_16_SRC_MOV: case OPC1_16_SRC_MOV:
case OPC1_16_SRC_MOV_A: case OPC1_16_SRC_MOV_A:
case OPC1_16_SRC_MOV_E:
case OPC1_16_SRC_SH: case OPC1_16_SRC_SH:
case OPC1_16_SRC_SHA: case OPC1_16_SRC_SHA:
decode_src_opc(ctx, op1); decode_src_opc(env, ctx, op1);
break; break;
/* SRR-format */ /* SRR-format */
case OPC1_16_SRR_ADD: case OPC1_16_SRR_ADD: