mirror of https://github.com/xqemu/xqemu.git
target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -3485,7 +3485,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
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* Functions for decoding instructions
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* Functions for decoding instructions
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*/
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*/
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static void decode_src_opc(DisasContext *ctx, int op1)
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static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
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{
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{
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int r1;
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int r1;
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int32_t const4;
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int32_t const4;
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@ -3546,6 +3546,12 @@ static void decode_src_opc(DisasContext *ctx, int op1)
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const4 = MASK_OP_SRC_CONST4(ctx->opcode);
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const4 = MASK_OP_SRC_CONST4(ctx->opcode);
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tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
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tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
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break;
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break;
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case OPC1_16_SRC_MOV_E:
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if (tricore_feature(env, TRICORE_FEATURE_16)) {
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tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
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tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
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} /* TODO: else raise illegal opcode trap */
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break;
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case OPC1_16_SRC_SH:
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case OPC1_16_SRC_SH:
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gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
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gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
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break;
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break;
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@ -3883,9 +3889,10 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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case OPC1_16_SRC_LT:
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case OPC1_16_SRC_LT:
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case OPC1_16_SRC_MOV:
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case OPC1_16_SRC_MOV:
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case OPC1_16_SRC_MOV_A:
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case OPC1_16_SRC_MOV_A:
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case OPC1_16_SRC_MOV_E:
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case OPC1_16_SRC_SH:
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case OPC1_16_SRC_SH:
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case OPC1_16_SRC_SHA:
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case OPC1_16_SRC_SHA:
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decode_src_opc(ctx, op1);
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decode_src_opc(env, ctx, op1);
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break;
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break;
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/* SRR-format */
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/* SRR-format */
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case OPC1_16_SRR_ADD:
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case OPC1_16_SRR_ADD:
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