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ppc: fix MSR_ME handling for system reset interrupt 

Power ISA specifies ME bit handling for system reset interrupt:

    if the interrupt occurred while the thread was in power-saving
    mode, set to 1; otherwise not altered

Power ISA 3.0, section 6.5 "Interrupt Definitions", Figure 64.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nicholas Piggin 2016-10-20 17:59:10 +11:00 committed by David Gibson
parent e3403258a2
commit f85bcec31e
1 changed files with 2 additions and 2 deletions
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4
target-ppc/excp_helper.c
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@ -385,11 +385,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
srr1 = SPR_BOOKE_CSRR1; srr1 = SPR_BOOKE_CSRR1;
break; break;
case POWERPC_EXCP_RESET: /* System reset exception */ case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) { if (msr_pow) {
/* indicate that we resumed from power save mode */ /* indicate that we resumed from power save mode */
msr |= 0x10000; msr |= 0x10000;
} else { new_msr |= ((target_ulong)1 << MSR_ME);
new_msr &= ~((target_ulong)1 << MSR_ME);
} }
new_msr |= (target_ulong)MSR_HVB; new_msr |= (target_ulong)MSR_HVB;