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target-sparc: Use DisasCompare and movcond in MOVCC 

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2012-10-05 16:55:00 -07:00 committed by Blue Swirl
parent 7e480893cc
commit f52879b441
1 changed files with 20 additions and 24 deletions
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44
target-sparc/translate.c
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@ -4075,38 +4075,34 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
{ {
int cc = GET_FIELD_SP(insn, 11, 12); int cc = GET_FIELD_SP(insn, 11, 12);
int cond = GET_FIELD_SP(insn, 14, 17); int cond = GET_FIELD_SP(insn, 14, 17);
TCGv r_cond; DisasCompare cmp;
int l1;
r_cond = tcg_temp_new();
if (insn & (1 << 18)) { if (insn & (1 << 18)) {
if (cc == 0) if (cc == 0) {
gen_cond(r_cond, 0, cond, dc); gen_compare(&cmp, 0, cond, dc);
else if (cc == 2) } else if (cc == 2) {
gen_cond(r_cond, 1, cond, dc); gen_compare(&cmp, 1, cond, dc);
else } else {
goto illegal_insn; goto illegal_insn;
}
} else { } else {
gen_fcond(r_cond, cc, cond); gen_fcompare(&cmp, cc, cond);
} }
l1 = gen_new_label(); /* The get_src2 above loaded the normal 13-bit
immediate field, not the 11-bit field we have
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); in movcc. But it did handle the reg case. */
if (IS_IMM) { /* immediate */ if (IS_IMM) {
TCGv r_const;
simm = GET_FIELD_SPs(insn, 0, 10); simm = GET_FIELD_SPs(insn, 0, 10);
r_const = tcg_const_tl(simm); tcg_gen_movi_tl(cpu_src2, simm);
gen_movl_TN_reg(rd, r_const);
tcg_temp_free(r_const);
} else {
rs2 = GET_FIELD_SP(insn, 0, 4);
gen_movl_reg_TN(rs2, cpu_tmp0);
gen_movl_TN_reg(rd, cpu_tmp0);
} }
gen_set_label(l1);
tcg_temp_free(r_cond); gen_movl_reg_TN(rd, cpu_dst);
tcg_gen_movcond_tl(cmp.cond, cpu_dst,
cmp.c1, cmp.c2,
cpu_src2, cpu_dst);
free_compare(&cmp);
gen_movl_TN_reg(rd, cpu_dst);
break; break;
} }
case 0x2d: /* V9 sdivx */ case 0x2d: /* V9 sdivx */