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target-mips: Avoid shifting left into sign bit 

Add U suffix to various places where we shift a 1 left by 31,
to avoid undefined behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Peter Maydell 2014-03-17 16:00:34 +00:00 committed by Michael Tokarev
parent d9631b90da
commit f45cb2f43f
4 changed files with 17 additions and 17 deletions
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2
target-mips/cpu.h
View File

@ -775,7 +775,7 @@ static inline void compute_hflags(CPUMIPSState *env)
and disable the MIPS IV extensions to the MIPS III ISA. and disable the MIPS IV extensions to the MIPS III ISA.
Some other MIPS IV CPUs ignore the bit, so the check here Some other MIPS IV CPUs ignore the bit, so the check here
would be too restrictive for them. */ would be too restrictive for them. */
if (env->CP0_Status & (1 << CP0St_CU3)) { if (env->CP0_Status & (1U << CP0St_CU3)) {
env->hflags |= MIPS_HFLAG_COP1X; env->hflags |= MIPS_HFLAG_COP1X;
} }
} }

8
target-mips/helper.c
View File

@ -458,7 +458,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags &= ~(MIPS_HFLAG_KSU); env->hflags &= ~(MIPS_HFLAG_KSU);
/* EJTAG probe trap enable is not implemented... */ /* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL))) if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD); env->CP0_Cause &= ~(1U << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00480; env->active_tc.PC = (int32_t)0xBFC00480;
set_hflags_for_handler(env); set_hflags_for_handler(env);
break; break;
@ -478,7 +478,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU); env->hflags &= ~(MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL))) if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD); env->CP0_Cause &= ~(1U << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00000; env->active_tc.PC = (int32_t)0xBFC00000;
set_hflags_for_handler(env); set_hflags_for_handler(env);
break; break;
@ -616,9 +616,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
if (!(env->CP0_Status & (1 << CP0St_EXL))) { if (!(env->CP0_Status & (1 << CP0St_EXL))) {
env->CP0_EPC = exception_resume_pc(env); env->CP0_EPC = exception_resume_pc(env);
if (env->hflags & MIPS_HFLAG_BMASK) { if (env->hflags & MIPS_HFLAG_BMASK) {
env->CP0_Cause |= (1 << CP0Ca_BD); env->CP0_Cause |= (1U << CP0Ca_BD);
} else { } else {
env->CP0_Cause &= ~(1 << CP0Ca_BD); env->CP0_Cause &= ~(1U << CP0Ca_BD);
} }
env->CP0_Status |= (1 << CP0St_EXL); env->CP0_Status |= (1 << CP0St_EXL);
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;

2
target-mips/op_helper.c
View File

@ -648,7 +648,7 @@ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
{ {
uint32_t status; uint32_t status;
uint32_t tcu, tmx, tasid, tksu; uint32_t tcu, tmx, tasid, tksu;
uint32_t mask = ((1 << CP0St_CU3) uint32_t mask = ((1U << CP0St_CU3)
| (1 << CP0St_CU2) | (1 << CP0St_CU2)
| (1 << CP0St_CU1) | (1 << CP0St_CU1)
| (1 << CP0St_CU0) | (1 << CP0St_CU0)

22
target-mips/translate_init.c
View File

@ -22,20 +22,20 @@
/* Have config1, uncached coherency */ /* Have config1, uncached coherency */
#define MIPS_CONFIG0 \ #define MIPS_CONFIG0 \
((1 << CP0C0_M) | (0x2 << CP0C0_K0)) ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
/* Have config2, no coprocessor2 attached, no MDMX support attached, /* Have config2, no coprocessor2 attached, no MDMX support attached,
no performance counters, watch registers present, no performance counters, watch registers present,
no code compression, EJTAG present, no FPU */ no code compression, EJTAG present, no FPU */
#define MIPS_CONFIG1 \ #define MIPS_CONFIG1 \
((1 << CP0C1_M) | \ ((1U << CP0C1_M) | \
(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
(0 << CP0C1_FP)) (0 << CP0C1_FP))
/* Have config3, no tertiary/secondary caches implemented */ /* Have config3, no tertiary/secondary caches implemented */
#define MIPS_CONFIG2 \ #define MIPS_CONFIG2 \
((1 << CP0C2_M)) ((1U << CP0C2_M))
/* No config4, no DSP ASE, no large physaddr (PABITS), /* No config4, no DSP ASE, no large physaddr (PABITS),
no external interrupt controller, no vectored interrupts, no external interrupt controller, no vectored interrupts,
@ -301,16 +301,16 @@ static const mips_def_t mips_defs[] =
(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
.CP0_SRSConf0_rw_bitmask = 0x3fffffff, .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
.CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
.CP0_SRSConf1_rw_bitmask = 0x3fffffff, .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
.CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
(0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
.CP0_SRSConf2_rw_bitmask = 0x3fffffff, .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
.CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
(0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
.CP0_SRSConf3_rw_bitmask = 0x3fffffff, .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
.CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
(0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
.CP0_SRSConf4_rw_bitmask = 0x3fffffff, .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
@ -355,8 +355,8 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA), (1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M), .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
.CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
.CP0_Config4_rw_bitmask = 0, .CP0_Config4_rw_bitmask = 0,
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
@ -670,7 +670,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
programmable cache partitioning implemented, number of allocatable programmable cache partitioning implemented, number of allocatable
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
implemented, 5 TCs implemented. */ implemented, 5 TCs implemented. */
env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
// TODO: actually do 2 VPEs. // TODO: actually do 2 VPEs.
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
@ -684,7 +684,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support, /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
(0x1 << CP0MVPC1_PCP1); (0x1 << CP0MVPC1_PCP1);
} }