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ahci: fix spacing damage on ahci_port_write 

Churn.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180531222835.16558-5-jsnow@redhat.com
[Fix patchew/checkpatch nit. --js]
Signed-off-by: John Snow <jsnow@redhat.com>
This commit is contained in:
John Snow 2018-06-08 13:17:36 -04:00
parent e538916366
commit f1123e4b5c
1 changed files with 71 additions and 71 deletions
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142
hw/ide/ahci.c
View File

@ -279,85 +279,85 @@ static int ahci_cond_start_engines(AHCIDevice *ad)
return 0; return 0;
} }
static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
{ {
AHCIPortRegs *pr = &s->dev[port].port_regs; AHCIPortRegs *pr = &s->dev[port].port_regs;
trace_ahci_port_write(s, port, offset, val); trace_ahci_port_write(s, port, offset, val);
switch (offset) { switch (offset) {
case PORT_LST_ADDR: case PORT_LST_ADDR:
pr->lst_addr = val; pr->lst_addr = val;
break; break;
case PORT_LST_ADDR_HI: case PORT_LST_ADDR_HI:
pr->lst_addr_hi = val; pr->lst_addr_hi = val;
break; break;
case PORT_FIS_ADDR: case PORT_FIS_ADDR:
pr->fis_addr = val; pr->fis_addr = val;
break; break;
case PORT_FIS_ADDR_HI: case PORT_FIS_ADDR_HI:
pr->fis_addr_hi = val; pr->fis_addr_hi = val;
break; break;
case PORT_IRQ_STAT: case PORT_IRQ_STAT:
pr->irq_stat &= ~val; pr->irq_stat &= ~val;
ahci_check_irq(s); ahci_check_irq(s);
break; break;
case PORT_IRQ_MASK: case PORT_IRQ_MASK:
pr->irq_mask = val & 0xfdc000ff; pr->irq_mask = val & 0xfdc000ff;
ahci_check_irq(s); ahci_check_irq(s);
break; break;
case PORT_CMD: case PORT_CMD:
/* Block any Read-only fields from being set; /* Block any Read-only fields from being set;
* including LIST_ON and FIS_ON. * including LIST_ON and FIS_ON.
* The spec requires to set ICC bits to zero after the ICC change * The spec requires to set ICC bits to zero after the ICC change
* is done. We don't support ICC state changes, therefore always * is done. We don't support ICC state changes, therefore always
* force the ICC bits to zero. * force the ICC bits to zero.
*/ */
pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |
(val & ~(PORT_CMD_RO_MASK|PORT_CMD_ICC_MASK)); (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK));
/* Check FIS RX and CLB engines */ /* Check FIS RX and CLB engines */
ahci_cond_start_engines(&s->dev[port]); ahci_cond_start_engines(&s->dev[port]);
/* XXX usually the FIS would be pending on the bus here and /* XXX usually the FIS would be pending on the bus here and
issuing deferred until the OS enables FIS receival. issuing deferred until the OS enables FIS receival.
Instead, we only submit it once - which works in most Instead, we only submit it once - which works in most
cases, but is a hack. */ cases, but is a hack. */
if ((pr->cmd & PORT_CMD_FIS_ON) && if ((pr->cmd & PORT_CMD_FIS_ON) &&
!s->dev[port].init_d2h_sent) { !s->dev[port].init_d2h_sent) {
ahci_init_d2h(&s->dev[port]); ahci_init_d2h(&s->dev[port]);
} }
check_cmd(s, port); check_cmd(s, port);
break; break;
case PORT_TFDATA: case PORT_TFDATA:
/* Read Only. */ /* Read Only. */
break; break;
case PORT_SIG: case PORT_SIG:
/* Read Only */ /* Read Only */
break; break;
case PORT_SCR_STAT: case PORT_SCR_STAT:
/* Read Only */ /* Read Only */
break; break;
case PORT_SCR_CTL: case PORT_SCR_CTL:
if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) && if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
((val & AHCI_SCR_SCTL_DET) == 0)) { ((val & AHCI_SCR_SCTL_DET) == 0)) {
ahci_reset_port(s, port); ahci_reset_port(s, port);
} }
pr->scr_ctl = val; pr->scr_ctl = val;
break; break;
case PORT_SCR_ERR: case PORT_SCR_ERR:
pr->scr_err &= ~val; pr->scr_err &= ~val;
break; break;
case PORT_SCR_ACT: case PORT_SCR_ACT:
/* RW1 */ /* RW1 */
pr->scr_act |= val; pr->scr_act |= val;
break; break;
case PORT_CMD_ISSUE: case PORT_CMD_ISSUE:
pr->cmd_issue |= val; pr->cmd_issue |= val;
check_cmd(s, port); check_cmd(s, port);
break; break;
default: default:
break; break;
} }
} }