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target-arm: Convert debug registers to cp_reginfo 

Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the
cp_reginfo scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-06-20 11:57:09 +00:00
parent 2ceb98c007
commit e9aa6c2148
2 changed files with 25 additions and 28 deletions
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25
target-arm/helper.c
View File

@ -56,6 +56,27 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
return 0; return 0;
} }
static const ARMCPRegInfo cp_reginfo[] = {
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
* version" bits will read as a reserved value, which should cause
* Linux to not try to use the debug hardware.
*/
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
static const ARMCPRegInfo v7_cp_reginfo[] = {
/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
* debug components
*/
{ .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
void register_cp_regs_for_features(ARMCPU *cpu) void register_cp_regs_for_features(ARMCPU *cpu)
{ {
/* Register all the coprocessor registers based on feature bits */ /* Register all the coprocessor registers based on feature bits */
@ -65,6 +86,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
return; return;
} }
define_arm_cp_regs(cpu, cp_reginfo);
if (arm_feature(env, ARM_FEATURE_V7)) {
define_arm_cp_regs(cpu, v7_cp_reginfo);
}
} }
ARMCPU *cpu_arm_init(const char *cpu_model) ARMCPU *cpu_arm_init(const char *cpu_model)

28
target-arm/translate.c
View File

@ -6364,34 +6364,6 @@ static int disas_cp14_read(CPUARMState * env, DisasContext *s, uint32_t insn)
int rt = (insn >> 12) & 0xf; int rt = (insn >> 12) & 0xf;
TCGv tmp; TCGv tmp;
/* Minimal set of debug registers, since we don't support debug */
if (op1 == 0 && crn == 0 && op2 == 0) {
switch (crm) {
case 0:
/* DBGDIDR: just RAZ. In particular this means the
* "debug architecture version" bits will read as
* a reserved value, which should cause Linux to
* not try to use the debug hardware.
*/
tmp = tcg_const_i32(0);
store_reg(s, rt, tmp);
return 0;
case 1:
case 2:
/* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
* don't implement memory mapped debug components
*/
if (ENABLE_ARCH_7) {
tmp = tcg_const_i32(0);
store_reg(s, rt, tmp);
return 0;
}
break;
default:
break;
}
}
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
/* TEECR */ /* TEECR */