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target-ppc: fix SPE evcmp* instructions 

The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit
position.  Because of this, the SPE evcmp* family of instructions would
store values in the result condition register that were also off by one
bit position.

Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Nathan Froyd 2010-02-23 11:55:14 -08:00 committed by Aurelien Jarno
parent e3b283e94a
commit e6bba2ef49
1 changed files with 4 additions and 4 deletions
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8
target-ppc/cpu.h
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@ -834,10 +834,10 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#define CRF_GT 2
#define CRF_EQ 1
#define CRF_SO 0
#define CRF_CH (1 << 4)
#define CRF_CL (1 << 3)
#define CRF_CH_OR_CL (1 << 2)
#define CRF_CH_AND_CL (1 << 1)
#define CRF_CH (1 << CRF_LT)
#define CRF_CL (1 << CRF_GT)
#define CRF_CH_OR_CL (1 << CRF_EQ)
#define CRF_CH_AND_CL (1 << CRF_SO)
/* XER definitions */
#define XER_SO 31