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target-alpha: fix extlh instruction 

The extlh instruction on Alpha currently doesn't work properly.
It's a combination of a cut/paste bug (16 where it should be 32) as well
as a "shift by 64" bug.

Signed-off-by: Vince Weaver <vince@csl.cornell.edu>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Vince Weaver 2009-09-17 15:28:52 -04:00 committed by Aurelien Jarno
parent 7fd6bf7dae
commit dbf9580588
1 changed files with 6 additions and 5 deletions
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11
target-alpha/translate.c
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@ -524,14 +524,15 @@ static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
else else
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]); tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
} else { } else {
TCGv tmp1, tmp2; TCGv tmp1;
tmp1 = tcg_temp_new(); tmp1 = tcg_temp_new();
tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7); tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
tcg_gen_shli_i64(tmp1, tmp1, 3); tcg_gen_shli_i64(tmp1, tmp1, 3);
tmp2 = tcg_const_i64(64); tcg_gen_neg_i64(tmp1, tmp1);
tcg_gen_sub_i64(tmp1, tmp2, tmp1); tcg_gen_andi_i64(tmp1, tmp1, 0x3f);
tcg_temp_free(tmp2);
tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1); tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
tcg_temp_free(tmp1); tcg_temp_free(tmp1);
} }
if (tcg_gen_ext_i64) if (tcg_gen_ext_i64)
@ -1316,7 +1317,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x6A: case 0x6A:
/* EXTLH */ /* EXTLH */
gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); gen_ext_h(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit);
break; break;
case 0x72: case 0x72:
/* MSKQH */ /* MSKQH */