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target-ppc: VSX Stage 4: Add VSX 2.07 Flag 

This patch adds a flag to identify those VSX instructions that are
new to Power ISA V2.07.  The flag is added to the Power 8 processor
initialization so that the P8 models understand how to decode and
emulate instructions in this category.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Tom Musta 2014-01-15 08:10:28 -06:00 committed by Alexander Graf
parent 88e33d08c9
commit dbcc48fa8f
2 changed files with 4 additions and 2 deletions
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4
target-ppc/cpu.h
View File

@ -1875,9 +1875,11 @@ enum {
PPC2_DBRX = 0x0000000000000010ULL, PPC2_DBRX = 0x0000000000000010ULL,
/* Book I 2.05 PowerPC specification */ /* Book I 2.05 PowerPC specification */
PPC2_ISA205 = 0x0000000000000020ULL, PPC2_ISA205 = 0x0000000000000020ULL,
/* VSX additions in ISA 2.07 */
PPC2_VSX207 = 0x0000000000000040ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205) PPC2_ISA205 | PPC2_VSX207)
}; };
/*****************************************************************************/ /*****************************************************************************/

2
target-ppc/translate_init.c
View File

@ -7144,7 +7144,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC | PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI | PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD; PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX; pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
pcc->msr_mask = 0x800000000284FF36ULL; pcc->msr_mask = 0x800000000284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06; pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)