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gen-icount: check cflags instead of use_icount global 

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2014-11-26 13:40:05 +03:00
parent bd79255d25
commit cd42d5b236
19 changed files with 21 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/exec/gen-icount.h
View File

@ -9,7 +9,7 @@ static TCGArg *icount_arg;
static int icount_label;
static int exitreq_label;
static inline void gen_tb_start(void)
static inline void gen_tb_start(TranslationBlock *tb)
{
TCGv_i32 count;
TCGv_i32 flag;
@ -21,7 +21,7 @@ static inline void gen_tb_start(void)
tcg_gen_brcondi_i32(TCG_COND_NE, flag, 0, exitreq_label);
tcg_temp_free_i32(flag);
if (!use_icount)
if (!(tb->cflags & CF_USE_ICOUNT))
return;
icount_label = gen_new_label();
@ -43,7 +43,7 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns)
gen_set_label(exitreq_label);
tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED);
if (use_icount) {
if (tb->cflags & CF_USE_ICOUNT) {
*icount_arg = num_insns;
gen_set_label(icount_label);
tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_ICOUNT_EXPIRED);

2
target-alpha/translate.c
View File

@ -2828,7 +2828,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
pc_mask = ~TARGET_PAGE_MASK;
}
gen_tb_start();
gen_tb_start(tb);
do {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {

2
target-arm/translate-a64.c
View File

@ -10962,7 +10962,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
max_insns = CF_COUNT_MASK;
}
gen_tb_start();
gen_tb_start(tb);
tcg_clear_temp_count();

2
target-arm/translate.c
View File

@ -11080,7 +11080,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_tb_start();
gen_tb_start(tb);
tcg_clear_temp_count();

2
target-cris/translate.c
View File

@ -3202,7 +3202,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
max_insns = CF_COUNT_MASK;
}
gen_tb_start();
gen_tb_start(tb);
do {
check_breakpoint(env, dc);

2
target-i386/translate.c
View File

@ -8002,7 +8002,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_tb_start();
gen_tb_start(tb);
for(;;) {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {

2
target-lm32/translate.c
View File

@ -1095,7 +1095,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
max_insns = CF_COUNT_MASK;
}
gen_tb_start();
gen_tb_start(tb);
do {
check_breakpoint(env, dc);

2
target-m68k/translate.c
View File

@ -3010,7 +3010,7 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_tb_start();
gen_tb_start(tb);
do {
pc_offset = dc->pc - pc_start;
gen_throws_exception = NULL;

2
target-microblaze/translate.c
View File

@ -1720,7 +1720,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_tb_start();
gen_tb_start(tb);
do
{
#if SIM_COMPAT

2
target-mips/translate.c
View File

@ -19130,7 +19130,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_tb_start();
gen_tb_start(tb);
while (ctx.bstate == BS_NONE) {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {

2
target-moxie/translate.c
View File

@ -843,7 +843,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
ctx.bstate = BS_NONE;
num_insns = 0;
gen_tb_start();
gen_tb_start(tb);
do {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {

2
target-openrisc/translate.c
View File

@ -1675,7 +1675,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
max_insns = CF_COUNT_MASK;
}
gen_tb_start();
gen_tb_start(tb);
do {
check_breakpoint(cpu, dc);

2
target-ppc/translate.c
View File

@ -11329,7 +11329,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_tb_start();
gen_tb_start(tb);
tcg_clear_temp_count();
/* Set env in case of segfault during code fetch */
while (ctx.exception == POWERPC_EXCP_NONE

2
target-s390x/translate.c
View File

@ -4779,7 +4779,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
max_insns = CF_COUNT_MASK;
}
gen_tb_start();
gen_tb_start(tb);
do {
if (search_pc) {

2
target-sh4/translate.c
View File

@ -1890,7 +1890,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_tb_start();
gen_tb_start(tb);
while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {

2
target-sparc/translate.c
View File

@ -5271,7 +5271,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_tb_start();
gen_tb_start(tb);
do {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {

2
target-tricore/translate.c
View File

@ -4069,7 +4069,7 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
ctx.mem_idx = cpu_mmu_index(env);
tcg_clear_temp_count();
gen_tb_start();
gen_tb_start(tb);
while (ctx.bstate == BS_NONE) {
ctx.opcode = cpu_ldl_code(env, ctx.pc);
decode_opc(env, &ctx, 0);

2
target-unicore32/translate.c
View File

@ -1917,7 +1917,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
}
#endif
gen_tb_start();
gen_tb_start(tb);
do {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {

2
target-xtensa/translate.c
View File

@ -3054,7 +3054,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
dc.next_icount = tcg_temp_local_new_i32();
}
gen_tb_start();
gen_tb_start(tb);
if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
tcg_gen_movi_i32(cpu_pc, dc.pc);