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petalogix_s2adsp1800: macro'd magic numbers 

defined macros for the addresses of the peripherals in machine model

Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Peter A. G. Crosthwaite 2012-03-04 21:03:53 +10:00 committed by Edgar E. Iglesias
parent 1f28fac87e
commit cba1fd3655
1 changed files with 13 additions and 7 deletions
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20
hw/petalogix_s3adsp1800_mmu.c
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@ -42,6 +42,13 @@
#define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb" #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
#define MEMORY_BASEADDR 0x90000000
#define FLASH_BASEADDR 0xa0000000
#define INTC_BASEADDR 0x81800000
#define TIMER_BASEADDR 0x83c00000
#define UARTLITE_BASEADDR 0x84000000
#define ETHLITE_BASEADDR 0x81000000
static void machine_cpu_reset(CPUState *env) static void machine_cpu_reset(CPUState *env)
{ {
/* FIXME: move to machine specfic cpu reset */ /* FIXME: move to machine specfic cpu reset */
@ -59,8 +66,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
CPUState *env; CPUState *env;
DriveInfo *dinfo; DriveInfo *dinfo;
int i; int i;
/* FIXME: remove harcoded magic numbers */ target_phys_addr_t ddr_base = MEMORY_BASEADDR;
target_phys_addr_t ddr_base = 0x90000000;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
@ -83,22 +89,22 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
memory_region_add_subregion(sysmem, ddr_base, phys_ram); memory_region_add_subregion(sysmem, ddr_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xa0000000, pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE, NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1); 1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = microblaze_pic_init_cpu(env); cpu_irq = microblaze_pic_init_cpu(env);
dev = xilinx_intc_create(0x81800000, cpu_irq[0], 2); dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 2);
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i); irq[i] = qdev_get_gpio_in(dev, i);
} }
sysbus_create_simple("xilinx,uartlite", 0x84000000, irq[3]); sysbus_create_simple("xilinx,uartlite", UARTLITE_BASEADDR, irq[3]);
/* 2 timers at irq 2 @ 62 Mhz. */ /* 2 timers at irq 2 @ 62 Mhz. */
xilinx_timer_create(0x83c00000, irq[0], 2, 62 * 1000000); xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000);
xilinx_ethlite_create(&nd_table[0], 0x81000000, irq[1], 0, 0); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);
microblaze_load_kernel(env, ddr_base, ram_size, microblaze_load_kernel(env, ddr_base, ram_size,
BINARY_DEVICE_TREE_FILE, machine_cpu_reset); BINARY_DEVICE_TREE_FILE, machine_cpu_reset);