mirror of https://github.com/xqemu/xqemu.git
apb: remove pci_apb_init() and instantiate APB device using qdev
By making the special_base and mem_base values qdev properties, we can move the remaining parts of pci_apb_init() into the pbm init() and realize() functions. This finally allows us to instantiate the APB directly using standard qdev create/init functions in sun4u.c. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Mark Cave-Ayland
parent
4272ad4018
commit
cacd05805e
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@ -611,66 +611,6 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
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pci_bridge_update_mappings(PCI_BRIDGE(br));
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}
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APBState *pci_apb_init(hwaddr special_base,
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hwaddr mem_base)
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{
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DeviceState *dev;
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SysBusDevice *s;
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PCIHostState *phb;
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APBState *d;
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IOMMUState *is;
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PCIDevice *pci_dev;
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/* Ultrasparc PBM main bus */
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dev = qdev_create(NULL, TYPE_APB);
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d = APB_DEVICE(dev);
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phb = PCI_HOST_BRIDGE(dev);
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phb->bus = pci_register_bus(DEVICE(phb), "pci",
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pci_apb_set_irq, pci_apb_map_irq, d,
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&d->pci_mmio,
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&d->pci_ioport,
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0, 32, TYPE_PCI_BUS);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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/* apb_config */
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sysbus_mmio_map(s, 0, special_base);
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/* PCI configuration space */
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sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
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/* pci_ioport */
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sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
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memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
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memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
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pci_create_simple(phb->bus, 0, "pbm-pci");
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/* APB IOMMU */
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is = &d->iommu;
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memset(is, 0, sizeof(IOMMUState));
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memory_region_init_iommu(&is->iommu, sizeof(is->iommu),
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TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(dev),
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"iommu-apb", UINT64_MAX);
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address_space_init(&is->iommu_as, MEMORY_REGION(&is->iommu), "pbm-as");
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pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is);
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/* APB secondary busses */
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
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TYPE_PBM_PCI_BRIDGE);
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d->bridgeB = PCI_BRIDGE(pci_dev);
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pci_bridge_map_irq(d->bridgeB, "pciB", pci_pbm_map_irq);
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qdev_init_nofail(&pci_dev->qdev);
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
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TYPE_PBM_PCI_BRIDGE);
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d->bridgeA = PCI_BRIDGE(pci_dev);
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pci_bridge_map_irq(d->bridgeA, "pciA", pci_pbm_map_irq);
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qdev_prop_set_bit(DEVICE(pci_dev), "busA", true);
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qdev_init_nofail(&pci_dev->qdev);
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return d;
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}
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static void pci_pbm_reset(DeviceState *d)
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{
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unsigned int i;
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@ -698,10 +638,62 @@ static const MemoryRegionOps pci_config_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int pci_pbm_init_device(DeviceState *dev)
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static void pci_pbm_realize(DeviceState *dev, Error **errp)
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{
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APBState *s = APB_DEVICE(dev);
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PCIHostState *phb = PCI_HOST_BRIDGE(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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PCIDevice *pci_dev;
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IOMMUState *is;
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/* apb_config */
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sysbus_mmio_map(sbd, 0, s->special_base);
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/* PCI configuration space */
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sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
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/* pci_ioport */
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sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL);
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memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
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memory_region_add_subregion(get_system_memory(), s->mem_base,
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&s->pci_mmio);
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phb->bus = pci_register_bus(dev, "pci",
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pci_apb_set_irq, pci_apb_map_irq, s,
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&s->pci_mmio,
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&s->pci_ioport,
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0, 32, TYPE_PCI_BUS);
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pci_create_simple(phb->bus, 0, "pbm-pci");
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/* APB IOMMU */
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is = &s->iommu;
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memset(is, 0, sizeof(IOMMUState));
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memory_region_init_iommu(&is->iommu, sizeof(is->iommu),
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TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(dev),
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"iommu-apb", UINT64_MAX);
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address_space_init(&is->iommu_as, MEMORY_REGION(&is->iommu), "pbm-as");
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pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is);
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/* APB secondary busses */
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
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TYPE_PBM_PCI_BRIDGE);
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s->bridgeB = PCI_BRIDGE(pci_dev);
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pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbm_map_irq);
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qdev_init_nofail(&pci_dev->qdev);
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pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
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TYPE_PBM_PCI_BRIDGE);
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s->bridgeA = PCI_BRIDGE(pci_dev);
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pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbm_map_irq);
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qdev_prop_set_bit(DEVICE(pci_dev), "busA", true);
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qdev_init_nofail(&pci_dev->qdev);
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}
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static void pci_pbm_init(Object *obj)
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{
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APBState *s = APB_DEVICE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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unsigned int i;
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for (i = 0; i < 8; i++) {
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@ -734,8 +726,6 @@ static int pci_pbm_init_device(DeviceState *dev)
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/* at region 2 */
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sysbus_init_mmio(sbd, &s->pci_ioport);
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return 0;
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}
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static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
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@ -774,12 +764,19 @@ static const TypeInfo pbm_pci_host_info = {
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},
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};
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static Property pbm_pci_host_properties[] = {
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DEFINE_PROP_UINT64("special-base", APBState, special_base, 0),
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DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pbm_host_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->init = pci_pbm_init_device;
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dc->realize = pci_pbm_realize;
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dc->reset = pci_pbm_reset;
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dc->props = pbm_pci_host_properties;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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}
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@ -787,6 +784,7 @@ static const TypeInfo pbm_host_info = {
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.name = TYPE_APB,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(APBState),
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.instance_init = pci_pbm_init,
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.class_init = pbm_host_class_init,
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};
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@ -502,7 +502,11 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
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prom_init(hwdef->prom_addr, bios_name);
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apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE);
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/* Init APB (PCI host bridge) */
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apb = APB_DEVICE(qdev_create(NULL, TYPE_APB));
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qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
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qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
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qdev_init_nofail(DEVICE(apb));
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/* Wire up PCI interrupts to CPU */
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for (i = 0; i < IVEC_MAX; i++) {
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@ -62,6 +62,8 @@ typedef struct IOMMUState {
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typedef struct APBState {
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PCIHostState parent_obj;
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hwaddr special_base;
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hwaddr mem_base;
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MemoryRegion apb_config;
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MemoryRegion pci_config;
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MemoryRegion pci_mmio;
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@ -93,6 +95,4 @@ typedef struct PBMPCIBridge {
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#define PBM_PCI_BRIDGE(obj) \
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OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
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APBState *pci_apb_init(hwaddr special_base,
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hwaddr mem_base);
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#endif
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