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target/alpha: Remove amask from tb->flags 

This value is constant for the cpu and does not need
to be stored within the TB.

Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2017-07-06 09:37:41 -10:00
parent 6887dc6700
commit c6d41b363c
2 changed files with 38 additions and 41 deletions
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9
target/alpha/cpu.h
View File

@ -487,14 +487,6 @@ enum {
TB_FLAGS_PAL_MODE = 1, TB_FLAGS_PAL_MODE = 1,
TB_FLAGS_FEN = 2, TB_FLAGS_FEN = 2,
TB_FLAGS_USER_MODE = 8, TB_FLAGS_USER_MODE = 8,
TB_FLAGS_AMASK_SHIFT = 4,
TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
}; };
static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
@ -513,7 +505,6 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
if (env->fen) { if (env->fen) {
flags |= TB_FLAGS_FEN; flags |= TB_FLAGS_FEN;
} }
flags |= env->amask << TB_FLAGS_AMASK_SHIFT;
*pflags = flags; *pflags = flags;
} }

70
target/alpha/translate.c
View File

@ -51,14 +51,15 @@ struct DisasContext {
#endif #endif
int mem_idx; int mem_idx;
/* implver and amask values for this CPU. */
int implver;
int amask;
/* Current rounding mode for this TB. */ /* Current rounding mode for this TB. */
int tb_rm; int tb_rm;
/* Current flush-to-zero setting for this TB. */ /* Current flush-to-zero setting for this TB. */
int tb_ftz; int tb_ftz;
/* implver value for this CPU. */
int implver;
/* The set of registers active in the current context. */ /* The set of registers active in the current context. */
TCGv *ir; TCGv *ir;
@ -1442,6 +1443,13 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
} \ } \
} while (0) } while (0)
#define REQUIRE_AMASK(FLAG) \
do { \
if ((ctx->amask & AMASK_##FLAG) == 0) { \
goto invalid_opc; \
} \
} while (0)
#define REQUIRE_TB_FLAG(FLAG) \ #define REQUIRE_TB_FLAG(FLAG) \
do { \ do { \
if ((ctx->tb->flags & (FLAG)) == 0) { \ if ((ctx->tb->flags & (FLAG)) == 0) { \
@ -1532,7 +1540,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
case 0x0A: case 0x0A:
/* LDBU */ /* LDBU */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); REQUIRE_AMASK(BWX);
gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
break; break;
case 0x0B: case 0x0B:
@ -1541,17 +1549,17 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x0C: case 0x0C:
/* LDWU */ /* LDWU */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); REQUIRE_AMASK(BWX);
gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);
break; break;
case 0x0D: case 0x0D:
/* STW */ /* STW */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); REQUIRE_AMASK(BWX);
gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0);
break; break;
case 0x0E: case 0x0E:
/* STB */ /* STB */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); REQUIRE_AMASK(BWX);
gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0);
break; break;
case 0x0F: case 0x0F:
@ -1832,10 +1840,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
case 0x61: case 0x61:
/* AMASK */ /* AMASK */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
{ tcg_gen_andi_i64(vc, vb, ~ctx->amask);
uint64_t amask = ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT;
tcg_gen_andi_i64(vc, vb, ~amask);
}
break; break;
case 0x64: case 0x64:
/* CMOVLE */ /* CMOVLE */
@ -2048,7 +2053,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x14: case 0x14:
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); REQUIRE_AMASK(FIX);
vc = dest_fpr(ctx, rc); vc = dest_fpr(ctx, rc);
switch (fpfn) { /* fn11 & 0x3F */ switch (fpfn) { /* fn11 & 0x3F */
case 0x04: case 0x04:
@ -2525,14 +2530,14 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
vc = dest_gpr(ctx, rc); vc = dest_gpr(ctx, rc);
if (fn7 == 0x70) { if (fn7 == 0x70) {
/* FTOIT */ /* FTOIT */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); REQUIRE_AMASK(FIX);
REQUIRE_REG_31(rb); REQUIRE_REG_31(rb);
va = load_fpr(ctx, ra); va = load_fpr(ctx, ra);
tcg_gen_mov_i64(vc, va); tcg_gen_mov_i64(vc, va);
break; break;
} else if (fn7 == 0x78) { } else if (fn7 == 0x78) {
/* FTOIS */ /* FTOIS */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); REQUIRE_AMASK(FIX);
REQUIRE_REG_31(rb); REQUIRE_REG_31(rb);
t32 = tcg_temp_new_i32(); t32 = tcg_temp_new_i32();
va = load_fpr(ctx, ra); va = load_fpr(ctx, ra);
@ -2546,117 +2551,117 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
switch (fn7) { switch (fn7) {
case 0x00: case 0x00:
/* SEXTB */ /* SEXTB */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); REQUIRE_AMASK(BWX);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
tcg_gen_ext8s_i64(vc, vb); tcg_gen_ext8s_i64(vc, vb);
break; break;
case 0x01: case 0x01:
/* SEXTW */ /* SEXTW */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); REQUIRE_AMASK(BWX);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
tcg_gen_ext16s_i64(vc, vb); tcg_gen_ext16s_i64(vc, vb);
break; break;
case 0x30: case 0x30:
/* CTPOP */ /* CTPOP */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); REQUIRE_AMASK(CIX);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_NO_LIT; REQUIRE_NO_LIT;
tcg_gen_ctpop_i64(vc, vb); tcg_gen_ctpop_i64(vc, vb);
break; break;
case 0x31: case 0x31:
/* PERR */ /* PERR */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
REQUIRE_NO_LIT; REQUIRE_NO_LIT;
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_perr(vc, va, vb); gen_helper_perr(vc, va, vb);
break; break;
case 0x32: case 0x32:
/* CTLZ */ /* CTLZ */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); REQUIRE_AMASK(CIX);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_NO_LIT; REQUIRE_NO_LIT;
tcg_gen_clzi_i64(vc, vb, 64); tcg_gen_clzi_i64(vc, vb, 64);
break; break;
case 0x33: case 0x33:
/* CTTZ */ /* CTTZ */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); REQUIRE_AMASK(CIX);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_NO_LIT; REQUIRE_NO_LIT;
tcg_gen_ctzi_i64(vc, vb, 64); tcg_gen_ctzi_i64(vc, vb, 64);
break; break;
case 0x34: case 0x34:
/* UNPKBW */ /* UNPKBW */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_NO_LIT; REQUIRE_NO_LIT;
gen_helper_unpkbw(vc, vb); gen_helper_unpkbw(vc, vb);
break; break;
case 0x35: case 0x35:
/* UNPKBL */ /* UNPKBL */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_NO_LIT; REQUIRE_NO_LIT;
gen_helper_unpkbl(vc, vb); gen_helper_unpkbl(vc, vb);
break; break;
case 0x36: case 0x36:
/* PKWB */ /* PKWB */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_NO_LIT; REQUIRE_NO_LIT;
gen_helper_pkwb(vc, vb); gen_helper_pkwb(vc, vb);
break; break;
case 0x37: case 0x37:
/* PKLB */ /* PKLB */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
REQUIRE_NO_LIT; REQUIRE_NO_LIT;
gen_helper_pklb(vc, vb); gen_helper_pklb(vc, vb);
break; break;
case 0x38: case 0x38:
/* MINSB8 */ /* MINSB8 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_minsb8(vc, va, vb); gen_helper_minsb8(vc, va, vb);
break; break;
case 0x39: case 0x39:
/* MINSW4 */ /* MINSW4 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_minsw4(vc, va, vb); gen_helper_minsw4(vc, va, vb);
break; break;
case 0x3A: case 0x3A:
/* MINUB8 */ /* MINUB8 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_minub8(vc, va, vb); gen_helper_minub8(vc, va, vb);
break; break;
case 0x3B: case 0x3B:
/* MINUW4 */ /* MINUW4 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_minuw4(vc, va, vb); gen_helper_minuw4(vc, va, vb);
break; break;
case 0x3C: case 0x3C:
/* MAXUB8 */ /* MAXUB8 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_maxub8(vc, va, vb); gen_helper_maxub8(vc, va, vb);
break; break;
case 0x3D: case 0x3D:
/* MAXUW4 */ /* MAXUW4 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_maxuw4(vc, va, vb); gen_helper_maxuw4(vc, va, vb);
break; break;
case 0x3E: case 0x3E:
/* MAXSB8 */ /* MAXSB8 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_maxsb8(vc, va, vb); gen_helper_maxsb8(vc, va, vb);
break; break;
case 0x3F: case 0x3F:
/* MAXSW4 */ /* MAXSW4 */
REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); REQUIRE_AMASK(MVI);
va = load_gpr(ctx, ra); va = load_gpr(ctx, ra);
gen_helper_maxsw4(vc, va, vb); gen_helper_maxsw4(vc, va, vb);
break; break;
@ -2929,6 +2934,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
ctx.pc = pc_start; ctx.pc = pc_start;
ctx.mem_idx = cpu_mmu_index(env, false); ctx.mem_idx = cpu_mmu_index(env, false);
ctx.implver = env->implver; ctx.implver = env->implver;
ctx.amask = env->amask;
ctx.singlestep_enabled = cs->singlestep_enabled; ctx.singlestep_enabled = cs->singlestep_enabled;
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY