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arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-28-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée 2018-03-01 11:05:56 +00:00 committed by Peter Maydell
parent d719cbc764
commit c625ff9507
1 changed files with 7 additions and 0 deletions
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7
target/arm/translate-a64.c
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@ -11388,6 +11388,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6f: /* FNEG */ case 0x6f: /* FNEG */
need_fpst = false; need_fpst = false;
break; break;
case 0x7d: /* FRSQRTE */
case 0x7f: /* FSQRT (vector) */ case 0x7f: /* FSQRT (vector) */
break; break;
default: default:
@ -11452,6 +11453,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6f: /* FNEG */ case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break; break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
@ -11504,6 +11508,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6f: /* FNEG */ case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break; break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x7f: /* FSQRT */ case 0x7f: /* FSQRT */
gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
break; break;