mirror of https://github.com/xqemu/xqemu.git
target/ppc: introduce get_avr64() and set_avr64() helpers for VMX register access
These helpers allow us to move AVR register values to/from the specified TCGv_i64
argument.
To prevent VMX helpers accessing the cpu_avr{l,h} arrays directly, add extra TCG
temporaries as required.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Mark Cave-Ayland
David Gibson
parent
1a404c91bd
commit
c4a18dbf52
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@ -6709,6 +6709,16 @@ static inline void set_fpr(int regno, TCGv_i64 src)
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tcg_gen_mov_i64(cpu_fpr[regno], src);
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}
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static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
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{
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tcg_gen_mov_i64(dst, (high ? cpu_avrh : cpu_avrl)[regno]);
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}
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static inline void set_avr64(int regno, TCGv_i64 src, bool high)
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{
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tcg_gen_mov_i64((high ? cpu_avrh : cpu_avrl)[regno], src);
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}
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#include "translate/fp-impl.inc.c"
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#include "translate/vmx-impl.inc.c"
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@ -18,52 +18,66 @@ static inline TCGv_ptr gen_avr_ptr(int reg)
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 avr; \
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_INT); \
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avr = tcg_temp_new_i64(); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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tcg_gen_andi_tl(EA, EA, ~0xf); \
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/* We only need to swap high and low halves. gen_qemu_ld64_i64 does \
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necessary 64-bit byteswap already. */ \
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if (ctx->le_mode) { \
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gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
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gen_qemu_ld64_i64(ctx, avr, EA); \
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set_avr64(rD(ctx->opcode), avr, false); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
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gen_qemu_ld64_i64(ctx, avr, EA); \
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set_avr64(rD(ctx->opcode), avr, true); \
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} else { \
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gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
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gen_qemu_ld64_i64(ctx, avr, EA); \
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set_avr64(rD(ctx->opcode), avr, true); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
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gen_qemu_ld64_i64(ctx, avr, EA); \
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set_avr64(rD(ctx->opcode), avr, false); \
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} \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(avr); \
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}
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#define GEN_VR_STX(name, opc2, opc3) \
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static void gen_st##name(DisasContext *ctx) \
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{ \
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TCGv EA; \
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TCGv_i64 avr; \
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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} \
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gen_set_access_type(ctx, ACCESS_INT); \
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avr = tcg_temp_new_i64(); \
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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tcg_gen_andi_tl(EA, EA, ~0xf); \
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/* We only need to swap high and low halves. gen_qemu_st64_i64 does \
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necessary 64-bit byteswap already. */ \
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if (ctx->le_mode) { \
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gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
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get_avr64(avr, rD(ctx->opcode), false); \
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gen_qemu_st64_i64(ctx, avr, EA); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
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get_avr64(avr, rD(ctx->opcode), true); \
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gen_qemu_st64_i64(ctx, avr, EA); \
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} else { \
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gen_qemu_st64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
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get_avr64(avr, rD(ctx->opcode), true); \
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gen_qemu_st64_i64(ctx, avr, EA); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_st64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
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get_avr64(avr, rD(ctx->opcode), false); \
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gen_qemu_st64_i64(ctx, avr, EA); \
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} \
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tcg_temp_free(EA); \
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tcg_temp_free_i64(avr); \
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}
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#define GEN_VR_LVE(name, opc2, opc3, size) \
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@ -159,15 +173,20 @@ static void gen_lvsr(DisasContext *ctx)
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static void gen_mfvscr(DisasContext *ctx)
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{
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TCGv_i32 t;
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TCGv_i64 avr;
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if (unlikely(!ctx->altivec_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VPU);
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return;
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}
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tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
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avr = tcg_temp_new_i64();
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tcg_gen_movi_i64(avr, 0);
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set_avr64(rD(ctx->opcode), avr, true);
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t = tcg_temp_new_i32();
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tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
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tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
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tcg_gen_extu_i32_i64(avr, t);
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set_avr64(rD(ctx->opcode), avr, false);
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tcg_temp_free_i32(t);
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tcg_temp_free_i64(avr);
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}
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static void gen_mtvscr(DisasContext *ctx)
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@ -185,9 +204,10 @@ static void gen_mtvscr(DisasContext *ctx)
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#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv_i64 t0 = tcg_temp_new_i64(); \
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TCGv_i64 t1 = tcg_temp_new_i64(); \
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TCGv_i64 t2 = tcg_temp_new_i64(); \
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TCGv_i64 t0; \
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TCGv_i64 t1; \
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TCGv_i64 t2; \
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TCGv_i64 avr; \
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TCGv_i64 ten, z; \
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\
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if (unlikely(!ctx->altivec_enabled)) { \
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@ -195,30 +215,43 @@ static void glue(gen_, name)(DisasContext *ctx) \
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return; \
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} \
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\
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t0 = tcg_temp_new_i64(); \
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t1 = tcg_temp_new_i64(); \
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t2 = tcg_temp_new_i64(); \
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avr = tcg_temp_new_i64(); \
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ten = tcg_const_i64(10); \
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z = tcg_const_i64(0); \
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\
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if (add_cin) { \
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tcg_gen_mulu2_i64(t0, t1, cpu_avrl[rA(ctx->opcode)], ten); \
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tcg_gen_andi_i64(t2, cpu_avrl[rB(ctx->opcode)], 0xF); \
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tcg_gen_add2_i64(cpu_avrl[rD(ctx->opcode)], t2, t0, t1, t2, z); \
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get_avr64(avr, rA(ctx->opcode), false); \
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tcg_gen_mulu2_i64(t0, t1, avr, ten); \
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get_avr64(avr, rB(ctx->opcode), false); \
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tcg_gen_andi_i64(t2, avr, 0xF); \
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tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
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set_avr64(rD(ctx->opcode), avr, false); \
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} else { \
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tcg_gen_mulu2_i64(cpu_avrl[rD(ctx->opcode)], t2, \
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cpu_avrl[rA(ctx->opcode)], ten); \
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get_avr64(avr, rA(ctx->opcode), false); \
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tcg_gen_mulu2_i64(avr, t2, avr, ten); \
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set_avr64(rD(ctx->opcode), avr, false); \
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} \
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\
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if (ret_carry) { \
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tcg_gen_mulu2_i64(t0, t1, cpu_avrh[rA(ctx->opcode)], ten); \
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tcg_gen_add2_i64(t0, cpu_avrl[rD(ctx->opcode)], t0, t1, t2, z); \
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tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); \
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get_avr64(avr, rA(ctx->opcode), true); \
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tcg_gen_mulu2_i64(t0, t1, avr, ten); \
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tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
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set_avr64(rD(ctx->opcode), avr, false); \
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set_avr64(rD(ctx->opcode), z, true); \
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} else { \
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tcg_gen_mul_i64(t0, cpu_avrh[rA(ctx->opcode)], ten); \
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tcg_gen_add_i64(cpu_avrh[rD(ctx->opcode)], t0, t2); \
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get_avr64(avr, rA(ctx->opcode), true); \
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tcg_gen_mul_i64(t0, avr, ten); \
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tcg_gen_add_i64(avr, t0, t2); \
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set_avr64(rD(ctx->opcode), avr, true); \
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} \
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\
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tcg_temp_free_i64(t0); \
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tcg_temp_free_i64(t1); \
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tcg_temp_free_i64(t2); \
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tcg_temp_free_i64(avr); \
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tcg_temp_free_i64(ten); \
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tcg_temp_free_i64(z); \
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} \
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@ -232,12 +265,31 @@ GEN_VX_VMUL10(vmul10ecuq, 1, 1);
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#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
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static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv_i64 t0; \
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TCGv_i64 t1; \
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TCGv_i64 avr; \
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\
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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} \
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tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
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tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
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t0 = tcg_temp_new_i64(); \
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t1 = tcg_temp_new_i64(); \
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avr = tcg_temp_new_i64(); \
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\
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get_avr64(t0, rA(ctx->opcode), true); \
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get_avr64(t1, rB(ctx->opcode), true); \
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tcg_op(avr, t0, t1); \
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set_avr64(rD(ctx->opcode), avr, true); \
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\
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get_avr64(t0, rA(ctx->opcode), false); \
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get_avr64(t1, rB(ctx->opcode), false); \
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tcg_op(avr, t0, t1); \
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set_avr64(rD(ctx->opcode), avr, false); \
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\
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tcg_temp_free_i64(t0); \
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tcg_temp_free_i64(t1); \
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tcg_temp_free_i64(avr); \
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}
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GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
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@ -406,6 +458,7 @@ GEN_VXFORM(vmrglw, 6, 6);
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static void gen_vmrgew(DisasContext *ctx)
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{
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TCGv_i64 tmp;
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TCGv_i64 avr;
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int VT, VA, VB;
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if (unlikely(!ctx->altivec_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VPU);
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@ -415,15 +468,28 @@ static void gen_vmrgew(DisasContext *ctx)
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VA = rA(ctx->opcode);
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VB = rB(ctx->opcode);
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tmp = tcg_temp_new_i64();
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tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
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tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
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tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
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tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
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avr = tcg_temp_new_i64();
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get_avr64(avr, VB, true);
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tcg_gen_shri_i64(tmp, avr, 32);
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get_avr64(avr, VA, true);
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tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
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set_avr64(VT, avr, true);
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get_avr64(avr, VB, false);
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tcg_gen_shri_i64(tmp, avr, 32);
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get_avr64(avr, VA, false);
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tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
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set_avr64(VT, avr, false);
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i64(avr);
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}
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static void gen_vmrgow(DisasContext *ctx)
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{
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TCGv_i64 t0, t1;
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TCGv_i64 avr;
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int VT, VA, VB;
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if (unlikely(!ctx->altivec_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VPU);
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@ -432,9 +498,23 @@ static void gen_vmrgow(DisasContext *ctx)
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VT = rD(ctx->opcode);
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VA = rA(ctx->opcode);
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VB = rB(ctx->opcode);
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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avr = tcg_temp_new_i64();
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tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
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tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
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get_avr64(t0, VB, true);
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get_avr64(t1, VA, true);
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tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
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set_avr64(VT, avr, true);
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get_avr64(t0, VB, false);
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get_avr64(t1, VA, false);
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tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
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set_avr64(VT, avr, false);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(avr);
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}
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GEN_VXFORM(vmuloub, 4, 0);
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@ -790,7 +870,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
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{ \
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TCGv_ptr rb, rd; \
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uint8_t uimm = UIMM4(ctx->opcode); \
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TCGv_i32 t0 = tcg_temp_new_i32(); \
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TCGv_i32 t0; \
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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@ -798,6 +878,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
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if (uimm > splat_max) { \
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uimm = 0; \
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} \
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t0 = tcg_temp_new_i32(); \
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tcg_gen_movi_i32(t0, uimm); \
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rb = gen_avr_ptr(rB(ctx->opcode)); \
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rd = gen_avr_ptr(rD(ctx->opcode)); \
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