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vmxcap: port to Python 3 

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2017-02-21 09:29:34 +01:00
parent cf0f7cf903
commit c3e31eaa21
1 changed files with 7 additions and 7 deletions
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14
scripts/kvm/vmxcap
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@ -27,9 +27,9 @@ MSR_IA32_VMX_VMFUNC = 0x491
class msr(object): class msr(object):
def __init__(self): def __init__(self):
try: try:
self.f = open('/dev/cpu/0/msr', 'r', 0) self.f = open('/dev/cpu/0/msr', 'rb', 0)
except: except:
self.f = open('/dev/msr0', 'r', 0) self.f = open('/dev/msr0', 'rb', 0)
def read(self, index, default = None): def read(self, index, default = None):
import struct import struct
self.f.seek(index) self.f.seek(index)
@ -49,7 +49,7 @@ class Control(object):
val = m.read(nr, 0) val = m.read(nr, 0)
return (val & 0xffffffff, val >> 32) return (val & 0xffffffff, val >> 32)
def show(self): def show(self):
print self.name print(self.name)
mbz, mb1 = self.read2(self.cap_msr) mbz, mb1 = self.read2(self.cap_msr)
tmbz, tmb1 = 0, 0 tmbz, tmb1 = 0, 0
if self.true_cap_msr: if self.true_cap_msr:
@ -69,7 +69,7 @@ class Control(object):
s = 'forced' s = 'forced'
elif one and zero: elif one and zero:
s = 'yes' s = 'yes'
print ' %-40s %s' % (self.bits[bit], s) print(' %-40s %s' % (self.bits[bit], s))
class Misc(object): class Misc(object):
def __init__(self, name, bits, msr): def __init__(self, name, bits, msr):
@ -77,9 +77,9 @@ class Misc(object):
self.bits = bits self.bits = bits
self.msr = msr self.msr = msr
def show(self): def show(self):
print self.name print(self.name)
value = msr().read(self.msr, 0) value = msr().read(self.msr, 0)
print ' Hex: 0x%x' % (value) print(' Hex: 0x%x' % (value))
def first_bit(key): def first_bit(key):
if type(key) is tuple: if type(key) is tuple:
return key[0] return key[0]
@ -94,7 +94,7 @@ class Misc(object):
def fmt(x): def fmt(x):
return { True: 'yes', False: 'no' }[x] return { True: 'yes', False: 'no' }[x]
v = (value >> lo) & ((1 << (hi - lo + 1)) - 1) v = (value >> lo) & ((1 << (hi - lo + 1)) - 1)
print ' %-40s %s' % (self.bits[bits], fmt(v)) print(' %-40s %s' % (self.bits[bits], fmt(v)))
controls = [ controls = [
Misc( Misc(