mirror of https://github.com/xqemu/xqemu.git
mac_dbdma: create DBDMAState instead of passing one array around
Signed-off-by: Juan Quintela <quintela@redhat.com>
This commit is contained in:
parent
9039d78e64
commit
c20df14b13
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@ -165,6 +165,10 @@ typedef struct DBDMA_channel {
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int processing;
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int processing;
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} DBDMA_channel;
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} DBDMA_channel;
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typedef struct {
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DBDMA_channel channels[DBDMA_CHANNELS];
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} DBDMAState;
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#ifdef DEBUG_DBDMA
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#ifdef DEBUG_DBDMA
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static void dump_dbdma_cmd(dbdma_cmd *cmd)
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static void dump_dbdma_cmd(dbdma_cmd *cmd)
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{
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{
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@ -617,31 +621,34 @@ static void channel_run(DBDMA_channel *ch)
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}
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}
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}
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}
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static void DBDMA_run (DBDMA_channel *ch)
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static void DBDMA_run(DBDMAState *s)
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{
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{
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int channel;
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int channel;
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for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
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for (channel = 0; channel < DBDMA_CHANNELS; channel++) {
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DBDMA_channel *ch = &s->channels[channel];
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uint32_t status = ch->regs[DBDMA_STATUS];
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uint32_t status = ch->regs[DBDMA_STATUS];
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if (!ch->processing && (status & RUN) && (status & ACTIVE))
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if (!ch->processing && (status & RUN) && (status & ACTIVE)) {
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channel_run(ch);
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channel_run(ch);
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}
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}
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}
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}
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}
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static void DBDMA_run_bh(void *opaque)
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static void DBDMA_run_bh(void *opaque)
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{
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{
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DBDMA_channel *ch = opaque;
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DBDMAState *s = opaque;
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DBDMA_DPRINTF("DBDMA_run_bh\n");
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DBDMA_DPRINTF("DBDMA_run_bh\n");
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DBDMA_run(ch);
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DBDMA_run(s);
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}
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}
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void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
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void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
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DBDMA_rw rw, DBDMA_flush flush,
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DBDMA_rw rw, DBDMA_flush flush,
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void *opaque)
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void *opaque)
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{
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{
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DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan;
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DBDMAState *s = dbdma;
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DBDMA_channel *ch = &s->channels[nchan];
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DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
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DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
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@ -700,7 +707,8 @@ static void dbdma_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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{
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{
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int channel = addr >> DBDMA_CHANNEL_SHIFT;
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int channel = addr >> DBDMA_CHANNEL_SHIFT;
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DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
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DBDMAState *s = opaque;
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DBDMA_channel *ch = &s->channels[channel];
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int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
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int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
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DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
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DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
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@ -749,7 +757,8 @@ static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
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{
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{
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uint32_t value;
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uint32_t value;
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int channel = addr >> DBDMA_CHANNEL_SHIFT;
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int channel = addr >> DBDMA_CHANNEL_SHIFT;
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DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
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DBDMAState *s = opaque;
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DBDMA_channel *ch = &s->channels[channel];
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int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
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int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
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value = ch->regs[reg];
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value = ch->regs[reg];
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@ -803,17 +812,17 @@ static CPUReadMemoryFunc * const dbdma_read[] = {
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static void dbdma_save(QEMUFile *f, void *opaque)
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static void dbdma_save(QEMUFile *f, void *opaque)
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{
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{
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DBDMA_channel *s = opaque;
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DBDMAState *s = opaque;
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unsigned int i, j;
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unsigned int i, j;
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for (i = 0; i < DBDMA_CHANNELS; i++)
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for (i = 0; i < DBDMA_CHANNELS; i++)
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for (j = 0; j < DBDMA_REGS; j++)
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for (j = 0; j < DBDMA_REGS; j++)
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qemu_put_be32s(f, &s[i].regs[j]);
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qemu_put_be32s(f, &s->channels[i].regs[j]);
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}
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}
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static int dbdma_load(QEMUFile *f, void *opaque, int version_id)
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static int dbdma_load(QEMUFile *f, void *opaque, int version_id)
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{
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{
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DBDMA_channel *s = opaque;
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DBDMAState *s = opaque;
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unsigned int i, j;
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unsigned int i, j;
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if (version_id != 2)
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if (version_id != 2)
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@ -821,25 +830,25 @@ static int dbdma_load(QEMUFile *f, void *opaque, int version_id)
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for (i = 0; i < DBDMA_CHANNELS; i++)
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for (i = 0; i < DBDMA_CHANNELS; i++)
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for (j = 0; j < DBDMA_REGS; j++)
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for (j = 0; j < DBDMA_REGS; j++)
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qemu_get_be32s(f, &s[i].regs[j]);
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qemu_get_be32s(f, &s->channels[i].regs[j]);
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return 0;
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return 0;
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}
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}
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static void dbdma_reset(void *opaque)
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static void dbdma_reset(void *opaque)
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{
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{
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DBDMA_channel *s = opaque;
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DBDMAState *s = opaque;
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int i;
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int i;
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for (i = 0; i < DBDMA_CHANNELS; i++)
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for (i = 0; i < DBDMA_CHANNELS; i++)
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memset(s[i].regs, 0, DBDMA_SIZE);
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memset(s->channels[i].regs, 0, DBDMA_SIZE);
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}
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}
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void* DBDMA_init (int *dbdma_mem_index)
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void* DBDMA_init (int *dbdma_mem_index)
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{
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{
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DBDMA_channel *s;
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DBDMAState *s;
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s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
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s = qemu_mallocz(sizeof(DBDMAState));
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*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s,
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*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s,
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DEVICE_LITTLE_ENDIAN);
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DEVICE_LITTLE_ENDIAN);
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