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Merge remote-tracking branch 'qemu-kvm-tmp/memory/batch' into staging

This commit is contained in:
Anthony Liguori 2011-09-22 10:27:14 -05:00
parent 27cdad67a1 2654c962b8
commit bdd2672109
12 changed files with 708 additions and 658 deletions
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90
hw/mips_jazz.c
View File

@ -52,44 +52,42 @@ static void main_cpu_reset(void *opaque)
cpu_reset(env);
}
static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
return cpu_inw(0x71);
}
static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void rtc_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
cpu_outw(0x71, val & 0xff);
}
static CPUReadMemoryFunc * const rtc_read[3] = {
rtc_readb,
rtc_readb,
rtc_readb,
static const MemoryRegionOps rtc_ops = {
.read = rtc_read,
.write = rtc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const rtc_write[3] = {
rtc_writeb,
rtc_writeb,
rtc_writeb,
};
static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
return 0xff;
}
static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
}
static CPUReadMemoryFunc * const dma_dummy_read[3] = {
NULL,
NULL,
NULL,
};
static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
dma_dummy_writeb,
dma_dummy_writeb,
dma_dummy_writeb,
static const MemoryRegionOps dma_dummy_ops = {
.read = dma_dummy_read,
.write = dma_dummy_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
@ -105,7 +103,7 @@ static void cpu_request_exit(void *opaque, int irq, int level)
}
static
void mips_jazz_init (ram_addr_t ram_size,
void mips_jazz_init (MemoryRegion *address_space, ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
@ -115,7 +113,8 @@ void mips_jazz_init (ram_addr_t ram_size,
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
int s_rtc, s_dma_dummy;
MemoryRegion *rtc = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev;
SysBusDevice *sysbus;
@ -123,8 +122,9 @@ void mips_jazz_init (ram_addr_t ram_size,
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
qemu_irq *cpu_exit_irq;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
if (cpu_model == NULL) {
@ -143,14 +143,15 @@ void mips_jazz_init (ram_addr_t ram_size,
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
memory_region_add_subregion(address_space, 0, ram);
bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
cpu_register_physical_memory(0x1fc00000LL,
MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
cpu_register_physical_memory(0xfff00000LL,
MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
@ -175,9 +176,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA devices */
i8259 = i8259_init(env->irq[4]);
@ -203,10 +203,11 @@ void mips_jazz_init (ram_addr_t ram_size,
sysbus_connect_irq(sysbus, 0, rc4030[3]);
{
/* Simple ROM, so user doesn't have to provide one */
ram_addr_t rom_offset = qemu_ram_alloc(NULL, "g364fb.rom", 0x80000);
uint8_t *rom = qemu_get_ram_ptr(rom_offset);
cpu_register_physical_memory(0x60000000, 0x80000,
rom_offset | IO_MEM_ROM);
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
@ -252,9 +253,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Real time clock */
rtc_init(1980, NULL);
s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
@ -299,7 +299,7 @@ void mips_magnum_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_MAGNUM);
}
static
@ -308,7 +308,7 @@ void mips_pica61_init (ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
mips_jazz_init(get_system_memory(), ram_size, cpu_model, JAZZ_PICA61);
}
static QEMUMachine mips_magnum_machine = {

53
hw/mips_malta.c
View File

@ -57,6 +57,9 @@
#define MAX_IDE_BUS 2
typedef struct {
MemoryRegion iomem;
MemoryRegion iomem_lo; /* 0 - 0x900 */
MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
uint32_t leds;
uint32_t brk;
uint32_t gpout;
@ -215,7 +218,8 @@ static void eeprom24c0x_write(int scl, int sda)
eeprom.sda = sda;
}
static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
MaltaFPGAState *s = opaque;
uint32_t val = 0;
@ -302,8 +306,8 @@ static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
return val;
}
static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
static void malta_fpga_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
MaltaFPGAState *s = opaque;
uint32_t saddr;
@ -328,7 +332,7 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
/* ASCIIWORD Register */
case 0x00410:
snprintf(s->display_text, 9, "%08X", val);
snprintf(s->display_text, 9, "%08X", (uint32_t)val);
malta_fpga_update_display(s);
break;
@ -388,16 +392,10 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
}
}
static CPUReadMemoryFunc * const malta_fpga_read[] = {
malta_fpga_readl,
malta_fpga_readl,
malta_fpga_readl
};
static CPUWriteMemoryFunc * const malta_fpga_write[] = {
malta_fpga_writel,
malta_fpga_writel,
malta_fpga_writel
static const MemoryRegionOps malta_fpga_ops = {
.read = malta_fpga_read,
.write = malta_fpga_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void malta_fpga_reset(void *opaque)
@ -429,20 +427,22 @@ static void malta_fpga_led_init(CharDriverState *chr)
qemu_chr_fe_printf(chr, "+--------+\r\n");
}
static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
int malta;
s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
malta = cpu_register_io_memory(malta_fpga_read,
malta_fpga_write, s,
DEVICE_NATIVE_ENDIAN);
memory_region_init_io(&s->iomem, &malta_fpga_ops, s,
"malta-fpga", 0x100000);
memory_region_init_alias(&s->iomem_lo, "malta-fpga",
&s->iomem, 0, 0x900);
memory_region_init_alias(&s->iomem_hi, "malta-fpga",
&s->iomem, 0xa00, 0x10000-0xa00);
cpu_register_physical_memory(base, 0x900, malta);
/* 0xa00 is less than a page, so will still get the right offsets. */
cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
memory_region_add_subregion(address_space, base, &s->iomem_lo);
memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
@ -771,8 +771,8 @@ void mips_malta_init (ram_addr_t ram_size,
{
char *filename;
pflash_t *fl;
ram_addr_t ram_offset;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios, *bios_alias = g_new(MemoryRegion, 1);
target_long bios_size;
int64_t kernel_entry;
@ -828,9 +828,8 @@ void mips_malta_init (ram_addr_t ram_size,
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "mips_malta.ram", ram_size);
memory_region_add_subregion(system_memory, 0, ram);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
@ -838,7 +837,7 @@ void mips_malta_init (ram_addr_t ram_size,
be = 0;
#endif
/* FPGA */
malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
malta_fpga_init(system_memory, 0x1f000000LL, env->irq[2], serial_hds[2]);
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
if (kernel_filename) {

15
hw/mips_mipssim.c
View File

@ -137,8 +137,9 @@ mips_mipssim_init (ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
CPUState *env;
ResetData *reset_info;
int bios_size;
@ -162,14 +163,14 @@ mips_mipssim_init (ram_addr_t ram_size,
qemu_register_reset(main_cpu_reset, reset_info);
/* Allocate RAM. */
ram_offset = qemu_ram_alloc(NULL, "mips_mipssim.ram", ram_size);
bios_offset = qemu_ram_alloc(NULL, "mips_mipssim.bios", BIOS_SIZE);
memory_region_init_ram(ram, NULL, "mips_mipssim.ram", ram_size);
memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE);
memory_region_set_readonly(bios, true);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
memory_region_add_subregion(address_space_mem, 0, ram);
/* Map the BIOS / boot exception handler. */
cpu_register_physical_memory(0x1fc00000LL,
BIOS_SIZE, bios_offset | IO_MEM_ROM);
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* Load a BIOS / boot exception handler image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;

39
hw/mips_r4k.c
View File

@ -42,8 +42,8 @@ static struct _loaderparams {
const char *initrd_filename;
} loaderparams;
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
static void mips_qemu_write (void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
qemu_system_reset_request ();
@ -51,25 +51,18 @@ static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
qemu_system_shutdown_request ();
}
static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr,
unsigned size)
{
return 0;
}
static CPUWriteMemoryFunc * const mips_qemu_write[] = {
&mips_qemu_writel,
&mips_qemu_writel,
&mips_qemu_writel,
static const MemoryRegionOps mips_qemu_ops = {
.read = mips_qemu_read,
.write = mips_qemu_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUReadMemoryFunc * const mips_qemu_read[] = {
&mips_qemu_readl,
&mips_qemu_readl,
&mips_qemu_readl,
};
static int mips_qemu_iomemtype = 0;
typedef struct ResetData {
CPUState *env;
uint64_t vector;
@ -163,8 +156,10 @@ void mips_r4k_init (ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
ram_addr_t ram_offset;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
int bios_size;
CPUState *env;
ResetData *reset_info;
@ -199,16 +194,12 @@ void mips_r4k_init (ram_addr_t ram_size,
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
ram_offset = qemu_ram_alloc(NULL, "mips_r4k.ram", ram_size);
memory_region_init_ram(ram, NULL, "mips_r4k.ram", ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
memory_region_add_subregion(address_space_mem, 0, ram);
if (!mips_qemu_iomemtype) {
mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
mips_qemu_write, NULL,
DEVICE_NATIVE_ENDIAN);
}
cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
memory_region_init_io(iomem, &mips_qemu_ops, NULL, "mips-qemu", 0x10000);
memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem);
/* Try to load a BIOS image. If this fails, we continue regardless,
but initialize the hardware ourselves. When a kernel gets

243
hw/musicpal.c
View File

@ -19,6 +19,7 @@
#include "console.h"
#include "i2c.h"
#include "blockdev.h"
#include "exec-memory.h"
#define MP_MISC_BASE 0x80002000
#define MP_MISC_SIZE 0x00001000
@ -142,6 +143,7 @@ typedef struct mv88w8618_rx_desc {
typedef struct mv88w8618_eth_state {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
uint32_t smir;
uint32_t icr;
@ -260,7 +262,8 @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
} while (desc_addr != s->tx_queue[queue_index]);
}
static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
mv88w8618_eth_state *s = opaque;
@ -302,7 +305,7 @@ static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
mv88w8618_eth_state *s = opaque;
@ -353,16 +356,10 @@ static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
}
}
static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
mv88w8618_eth_read,
mv88w8618_eth_read,
mv88w8618_eth_read
};
static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
mv88w8618_eth_write,
mv88w8618_eth_write,
mv88w8618_eth_write
static const MemoryRegionOps mv88w8618_eth_ops = {
.read = mv88w8618_eth_read,
.write = mv88w8618_eth_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void eth_cleanup(VLANClientState *nc)
@ -387,10 +384,9 @@ static int mv88w8618_eth_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
dev->qdev.info->name, dev->qdev.id, s);
s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
mv88w8618_eth_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
MP_ETH_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@ -444,6 +440,7 @@ static SysBusDeviceInfo mv88w8618_eth_info = {
typedef struct musicpal_lcd_state {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t brightness;
uint32_t mode;
uint32_t irqctrl;
@ -528,7 +525,8 @@ static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
s->brightness |= level << irq;
}
static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
musicpal_lcd_state *s = opaque;
@ -542,7 +540,7 @@ static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
musicpal_lcd_state *s = opaque;
@ -581,29 +579,21 @@ static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
}
}
static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
musicpal_lcd_read,
musicpal_lcd_read,
musicpal_lcd_read
};
static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
musicpal_lcd_write,
musicpal_lcd_write,
musicpal_lcd_write
static const MemoryRegionOps musicpal_lcd_ops = {
.read = musicpal_lcd_read,
.write = musicpal_lcd_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int musicpal_lcd_init(SysBusDevice *dev)
{
musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
int iomemtype;
s->brightness = 7;
iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
musicpal_lcd_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
"musicpal-lcd", MP_LCD_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
NULL, NULL, s);
@ -645,6 +635,7 @@ static SysBusDeviceInfo musicpal_lcd_info = {
typedef struct mv88w8618_pic_state
{
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t level;
uint32_t enabled;
qemu_irq parent_irq;
@ -667,7 +658,8 @@ static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
mv88w8618_pic_update(s);
}
static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
mv88w8618_pic_state *s = opaque;
@ -681,7 +673,7 @@ static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
mv88w8618_pic_state *s = opaque;
@ -707,29 +699,21 @@ static void mv88w8618_pic_reset(DeviceState *d)
s->enabled = 0;
}
static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
mv88w8618_pic_read,
mv88w8618_pic_read,
mv88w8618_pic_read
};
static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
mv88w8618_pic_write,
mv88w8618_pic_write,
mv88w8618_pic_write
static const MemoryRegionOps mv88w8618_pic_ops = {
.read = mv88w8618_pic_read,
.write = mv88w8618_pic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_pic_init(SysBusDevice *dev)
{
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
int iomemtype;
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
mv88w8618_pic_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
"musicpal-pic", MP_PIC_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@ -775,6 +759,7 @@ typedef struct mv88w8618_timer_state {
typedef struct mv88w8618_pit_state {
SysBusDevice busdev;
MemoryRegion iomem;
mv88w8618_timer_state timer[4];
} mv88w8618_pit_state;
@ -797,7 +782,8 @@ static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
s->ptimer = ptimer_init(bh);
}
static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
@ -813,7 +799,7 @@ static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
mv88w8618_pit_state *s = opaque;
mv88w8618_timer_state *t;
@ -864,21 +850,14 @@ static void mv88w8618_pit_reset(DeviceState *d)
}
}
static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
mv88w8618_pit_read,
mv88w8618_pit_read,
mv88w8618_pit_read
};
static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
mv88w8618_pit_write,
mv88w8618_pit_write,
mv88w8618_pit_write
static const MemoryRegionOps mv88w8618_pit_ops = {
.read = mv88w8618_pit_read,
.write = mv88w8618_pit_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_pit_init(SysBusDevice *dev)
{
int iomemtype;
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
int i;
@ -888,10 +867,9 @@ static int mv88w8618_pit_init(SysBusDevice *dev)
mv88w8618_timer_init(dev, &s->timer[i], 1000000);
}
iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
mv88w8618_pit_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
"musicpal-pit", MP_PIT_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@ -932,11 +910,13 @@ static SysBusDeviceInfo mv88w8618_pit_info = {
typedef struct mv88w8618_flashcfg_state {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t cfgr0;
} mv88w8618_flashcfg_state;
static uint32_t mv88w8618_flashcfg_read(void *opaque,
target_phys_addr_t offset)
static uint64_t mv88w8618_flashcfg_read(void *opaque,
target_phys_addr_t offset,
unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@ -950,7 +930,7 @@ static uint32_t mv88w8618_flashcfg_read(void *opaque,
}
static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@ -961,28 +941,20 @@ static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
}
}
static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
mv88w8618_flashcfg_read,
mv88w8618_flashcfg_read,
mv88w8618_flashcfg_read
};
static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
mv88w8618_flashcfg_write,
mv88w8618_flashcfg_write,
mv88w8618_flashcfg_write
static const MemoryRegionOps mv88w8618_flashcfg_ops = {
.read = mv88w8618_flashcfg_read,
.write = mv88w8618_flashcfg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_flashcfg_init(SysBusDevice *dev)
{
int iomemtype;
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
mv88w8618_flashcfg_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
"musicpal-flashcfg", MP_FLASHCFG_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
return 0;
}
@ -1009,7 +981,8 @@ static SysBusDeviceInfo mv88w8618_flashcfg_info = {
#define MP_BOARD_REVISION 0x31
static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
switch (offset) {
case MP_MISC_BOARD_REVISION:
@ -1021,37 +994,31 @@ static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
}
static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
musicpal_misc_read,
musicpal_misc_read,
musicpal_misc_read,
static const MemoryRegionOps musicpal_misc_ops = {
.read = musicpal_misc_read,
.write = musicpal_misc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
musicpal_misc_write,
musicpal_misc_write,
musicpal_misc_write,
};
static void musicpal_misc_init(void)
static void musicpal_misc_init(SysBusDevice *dev)
{
int iomemtype;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
musicpal_misc_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
"musicpal-misc", MP_MISC_SIZE);
sysbus_add_memory(dev, MP_MISC_BASE, iomem);
}
/* WLAN register offsets */
#define MP_WLAN_MAGIC1 0x11c
#define MP_WLAN_MAGIC2 0x124
static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
switch (offset) {
/* Workaround to allow loading the binary-only wlandrv.ko crap
@ -1067,30 +1034,23 @@ static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
}
static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
}
static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
mv88w8618_wlan_read,
mv88w8618_wlan_read,
mv88w8618_wlan_read,
};
static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
mv88w8618_wlan_write,
mv88w8618_wlan_write,
mv88w8618_wlan_write,
static const MemoryRegionOps mv88w8618_wlan_ops = {
.read = mv88w8618_wlan_read,
.write =mv88w8618_wlan_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int mv88w8618_wlan_init(SysBusDevice *dev)
{
int iomemtype;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
mv88w8618_wlan_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
"musicpal-wlan", MP_WLAN_SIZE);
sysbus_init_mmio_region(dev, iomem);
return 0;
}
@ -1118,6 +1078,7 @@ static int mv88w8618_wlan_init(SysBusDevice *dev)
typedef struct musicpal_gpio_state {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t lcd_brightness;
uint32_t out_state;
uint32_t in_state;
@ -1190,7 +1151,8 @@ static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
}
}
static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
musicpal_gpio_state *s = opaque;
@ -1229,7 +1191,7 @@ static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
}
static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
musicpal_gpio_state *s = opaque;
switch (offset) {
@ -1267,16 +1229,10 @@ static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
}
}
static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
musicpal_gpio_read,
musicpal_gpio_read,
musicpal_gpio_read,
};
static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
musicpal_gpio_write,
musicpal_gpio_write,
musicpal_gpio_write,
static const MemoryRegionOps musicpal_gpio_ops = {
.read = musicpal_gpio_read,
.write = musicpal_gpio_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void musicpal_gpio_reset(DeviceState *d)
@ -1295,14 +1251,12 @@ static void musicpal_gpio_reset(DeviceState *d)
static int musicpal_gpio_init(SysBusDevice *dev)
{
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
int iomemtype;
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
musicpal_gpio_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
"musicpal-gpio", MP_GPIO_SIZE);
sysbus_init_mmio_region(dev, &s->iomem);
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
@ -1501,7 +1455,9 @@ static void musicpal_init(ram_addr_t ram_size,
int i;
unsigned long flash_size;
DriveInfo *dinfo;
ram_addr_t sram_off;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model) {
cpu_model = "arm926";
@ -1514,12 +1470,11 @@ static void musicpal_init(ram_addr_t ram_size,
cpu_pic = arm_pic_init_cpu(env);
/* For now we use a fixed - the original - RAM size */
cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
qemu_ram_alloc(NULL, "musicpal.ram",
MP_RAM_DEFAULT_SIZE));
memory_region_init_ram(ram, NULL, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
memory_region_add_subregion(address_space_mem, 0, ram);
sram_off = qemu_ram_alloc(NULL, "musicpal.sram", MP_SRAM_SIZE);
cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE);
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
cpu_pic[ARM_PIC_CPU_IRQ]);
@ -1594,7 +1549,7 @@ static void musicpal_init(ram_addr_t ram_size,
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
musicpal_misc_init();
musicpal_misc_init(sysbus_from_qdev(dev));
dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);

32
hw/omap.h
View File

@ -678,7 +678,8 @@ void omap_uart_reset(struct omap_uart_s *s);
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
struct omap_mpuio_s;
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *system_memory,
target_phys_addr_t base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk);
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
@ -691,7 +692,8 @@ struct uWireSlave {
void *opaque;
};
struct omap_uwire_s;
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
target_phys_addr_t base,
qemu_irq *irq, qemu_irq dma, omap_clk clk);
void omap_uwire_attach(struct omap_uwire_s *s,
uWireSlave *slave, int chipselect);
@ -730,7 +732,8 @@ struct I2SCodec {
} in, out;
};
struct omap_mcbsp_s;
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
target_phys_addr_t base,
qemu_irq *irq, qemu_irq *dma, omap_clk clk);
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
@ -741,8 +744,7 @@ void omap_tap_init(struct omap_target_agent_s *ta,
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
struct omap_dma_lcd_channel_s *dma, omap_clk clk);
/* omap_dss.c */
struct rfbi_chip_s {
@ -826,6 +828,22 @@ struct omap_mpu_state_s {
qemu_irq wakeup;
MemoryRegion ulpd_pm_iomem;
MemoryRegion pin_cfg_iomem;
MemoryRegion id_iomem;
MemoryRegion id_iomem_e18;
MemoryRegion id_iomem_ed4;
MemoryRegion id_iomem_e20;
MemoryRegion mpui_iomem;
MemoryRegion tcmi_iomem;
MemoryRegion clkm_iomem;
MemoryRegion clkdsp_iomem;
MemoryRegion pwl_iomem;
MemoryRegion pwt_iomem;
MemoryRegion mpui_io_iomem;
MemoryRegion imif_ram;
MemoryRegion emiff_ram;
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
target_phys_addr_t offset);
@ -907,6 +925,7 @@ struct omap_mpu_state_s {
uint32_t tcmi_regs[17];
struct dpll_ctl_s {
MemoryRegion iomem;
uint16_t mode;
omap_clk dpll;
} dpll[3];
@ -947,7 +966,8 @@ struct omap_mpu_state_s {
};
/* omap1.c */
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
unsigned long sdram_size,
const char *core);
/* omap2.c */

865
hw/omap1.c
View File

File diff suppressed because it is too large Load Diff

6
hw/omap2.c
View File

@ -2284,8 +2284,10 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
s->port->addr_valid = omap2_validate_addr;
/* Register SDRAM and SRAM ports for fast DMA transfers. */
soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(q2_base),
OMAP2_Q2_BASE, s->sdram_size);
soc_dma_port_add_mem(s->dma, qemu_get_ram_ptr(sram_base),
OMAP2_SRAM_BASE, s->sram_size);
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
s->irq[0][OMAP_INT_24XX_UART1_IRQ],

7
hw/omap_lcdc.c
View File

@ -24,8 +24,6 @@
struct omap_lcd_panel_s {
qemu_irq irq;
DisplayState *state;
ram_addr_t imif_base;
ram_addr_t emiff_base;
int plm;
int tft;
@ -436,8 +434,7 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
}
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
struct omap_dma_lcd_channel_s *dma, omap_clk clk)
{
int iomemtype;
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
@ -445,8 +442,6 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
s->irq = irq;
s->dma = dma;
s->imif_base = imif_base;
s->emiff_base = emiff_base;
omap_lcdc_reset(s);
iomemtype = cpu_register_io_memory(omap_lcdc_readfn,

4
hw/omap_sx1.c
View File

@ -32,6 +32,7 @@
#include "arm-misc.h"
#include "flash.h"
#include "blockdev.h"
#include "exec-memory.h"
/*****************************************************************************/
/* Siemens SX1 Cellphone V1 */
@ -121,6 +122,7 @@ static void sx1_init(ram_addr_t ram_size,
const int version)
{
struct omap_mpu_state_s *cpu;
MemoryRegion *address_space = get_system_memory();
int io;
static uint32_t cs0val = 0x00213090;
static uint32_t cs1val = 0x00215070;
@ -135,7 +137,7 @@ static void sx1_init(ram_addr_t ram_size,
flash_size = flash2_size;
}
cpu = omap310_mpu_init(sx1_binfo.ram_size, cpu_model);
cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,

4
hw/palm.c
View File

@ -25,6 +25,7 @@
#include "arm-misc.h"
#include "devices.h"
#include "loader.h"
#include "exec-memory.h"
static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
{
@ -198,6 +199,7 @@ static void palmte_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
MemoryRegion *address_space_mem = get_system_memory();
struct omap_mpu_state_s *cpu;
int flash_size = 0x00800000;
int sdram_size = palmte_binfo.ram_size;
@ -209,7 +211,7 @@ static void palmte_init(ram_addr_t ram_size,
int rom_size, rom_loaded = 0;
DisplayState *ds = get_displaystate();
cpu = omap310_mpu_init(sdram_size, cpu_model);
cpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,

8
hw/soc_dma.h
View File

@ -18,6 +18,8 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "memory.h"
struct soc_dma_s;
struct soc_dma_ch_s;
typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len);
@ -105,9 +107,3 @@ static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
}
static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma,
ram_addr_t offset, target_phys_addr_t virt_base, size_t size)
{
return soc_dma_port_add_mem(dma, qemu_get_ram_ptr(offset), virt_base, size);
}