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target-mips: Copy restrictions from ext/ins to dext/dins 

The checks in dins is required to avoid triggering an assertion
in tcg_gen_deposit_tl.  The check in dext is just for completeness.
Fold the other D cases in via fallthru.

In this case the errant dins appears to be data, not code, as
translation failed to stop after a break insn.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Richard Henderson 2015-08-03 12:35:53 -07:00 committed by Leon Alrae
parent 060ebfef1a
commit b7f26e5239
1 changed files with 25 additions and 20 deletions
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43
target-mips/translate.c
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@ -4750,48 +4750,53 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
gen_load_gpr(t1, rs); gen_load_gpr(t1, rs);
switch (opc) { switch (opc) {
case OPC_EXT: case OPC_EXT:
if (lsb + msb > 31) if (lsb + msb > 31) {
goto fail; goto fail;
}
tcg_gen_shri_tl(t0, t1, lsb); tcg_gen_shri_tl(t0, t1, lsb);
if (msb != 31) { if (msb != 31) {
tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1); tcg_gen_andi_tl(t0, t0, (1U << (msb + 1)) - 1);
} else { } else {
tcg_gen_ext32s_tl(t0, t0); tcg_gen_ext32s_tl(t0, t0);
} }
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DEXTM:
tcg_gen_shri_tl(t0, t1, lsb);
if (msb != 31) {
tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1);
}
break;
case OPC_DEXTU: case OPC_DEXTU:
tcg_gen_shri_tl(t0, t1, lsb + 32); lsb += 32;
tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); goto do_dext;
break; case OPC_DEXTM:
msb += 32;
goto do_dext;
case OPC_DEXT: case OPC_DEXT:
do_dext:
if (lsb + msb > 63) {
goto fail;
}
tcg_gen_shri_tl(t0, t1, lsb); tcg_gen_shri_tl(t0, t1, lsb);
if (msb != 63) {
tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
}
break; break;
#endif #endif
case OPC_INS: case OPC_INS:
if (lsb > msb) if (lsb > msb) {
goto fail; goto fail;
}
gen_load_gpr(t0, rt); gen_load_gpr(t0, rt);
tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
tcg_gen_ext32s_tl(t0, t0); tcg_gen_ext32s_tl(t0, t0);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DINSM:
gen_load_gpr(t0, rt);
tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1);
break;
case OPC_DINSU: case OPC_DINSU:
gen_load_gpr(t0, rt); lsb += 32;
tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1); /* FALLTHRU */
break; case OPC_DINSM:
msb += 32;
/* FALLTHRU */
case OPC_DINS: case OPC_DINS:
if (lsb > msb) {
goto fail;
}
gen_load_gpr(t0, rt); gen_load_gpr(t0, rt);
tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
break; break;