mirror of https://github.com/xqemu/xqemu.git
tcg-mips: Enable direct chaining of TBs
Now that the code_gen_buffer is constrained to not cross 256mb regions, we are assured that we can use J to reach another TB. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -131,7 +131,7 @@ static inline void tlb_flush(CPUState *cpu, int flush_global)
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#if defined(__arm__) || defined(_ARCH_PPC) \
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#if defined(__arm__) || defined(_ARCH_PPC) \
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|| defined(__x86_64__) || defined(__i386__) \
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|| defined(__x86_64__) || defined(__i386__) \
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|| defined(__sparc__) || defined(__aarch64__) \
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|| defined(__sparc__) || defined(__aarch64__) \
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|| defined(__s390x__) \
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|| defined(__s390x__) || defined(__mips__) \
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|| defined(CONFIG_TCG_INTERPRETER)
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|| defined(CONFIG_TCG_INTERPRETER)
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#define USE_DIRECT_JUMP
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#define USE_DIRECT_JUMP
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#endif
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#endif
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@ -268,7 +268,7 @@ static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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#endif
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#endif
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}
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}
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#elif defined(__sparc__)
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#elif defined(__sparc__) || defined(__mips__)
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void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
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void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
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#else
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#else
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#error tb_set_jmp_target1 is missing
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#error tb_set_jmp_target1 is missing
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@ -1354,7 +1354,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_goto_tb:
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case INDEX_op_goto_tb:
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if (s->tb_jmp_offset) {
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if (s->tb_jmp_offset) {
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/* direct jump method */
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/* direct jump method */
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tcg_abort();
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s->tb_jmp_offset[a0] = tcg_current_code_size(s);
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/* Avoid clobbering the address during retranslation. */
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tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
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} else {
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} else {
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/* indirect jump method */
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/* indirect jump method */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
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@ -1805,3 +1807,10 @@ static void tcg_target_init(TCGContext *s)
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tcg_add_target_add_op_defs(mips_op_defs);
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tcg_add_target_add_op_defs(mips_op_defs);
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}
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}
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void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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{
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uint32_t *ptr = (uint32_t *)jmp_addr;
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*ptr = deposit32(*ptr, 0, 26, addr >> 2);
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flush_icache_range(jmp_addr, jmp_addr + 4);
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}
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