mirror of https://github.com/xqemu/xqemu.git
translator: merge max_insns into DisasContextBase
While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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6cd79443d3
commit
b542683d77
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@ -34,8 +34,6 @@ void translator_loop_temp_check(DisasContextBase *db)
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void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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CPUState *cpu, TranslationBlock *tb)
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CPUState *cpu, TranslationBlock *tb)
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{
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{
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int max_insns;
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/* Initialize DisasContext */
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/* Initialize DisasContext */
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db->tb = tb;
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db->tb = tb;
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db->pc_first = tb->pc;
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db->pc_first = tb->pc;
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@ -45,18 +43,18 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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db->singlestep_enabled = cpu->singlestep_enabled;
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db->singlestep_enabled = cpu->singlestep_enabled;
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/* Instruction counting */
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/* Instruction counting */
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max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
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db->max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
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if (max_insns == 0) {
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if (db->max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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db->max_insns = CF_COUNT_MASK;
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}
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}
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if (max_insns > TCG_MAX_INSNS) {
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if (db->max_insns > TCG_MAX_INSNS) {
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max_insns = TCG_MAX_INSNS;
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db->max_insns = TCG_MAX_INSNS;
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}
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}
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if (db->singlestep_enabled || singlestep) {
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if (db->singlestep_enabled || singlestep) {
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max_insns = 1;
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db->max_insns = 1;
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}
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}
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max_insns = ops->init_disas_context(db, cpu, max_insns);
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ops->init_disas_context(db, cpu);
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tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
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tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
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/* Reset the temp count so that we can identify leaks */
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/* Reset the temp count so that we can identify leaks */
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@ -95,7 +93,8 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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update db->pc_next and db->is_jmp to indicate what should be
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update db->pc_next and db->is_jmp to indicate what should be
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done next -- either exiting this loop or locate the start of
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done next -- either exiting this loop or locate the start of
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the next instruction. */
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the next instruction. */
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if (db->num_insns == max_insns && (tb_cflags(db->tb) & CF_LAST_IO)) {
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if (db->num_insns == db->max_insns
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&& (tb_cflags(db->tb) & CF_LAST_IO)) {
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/* Accept I/O on the last instruction. */
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/* Accept I/O on the last instruction. */
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gen_io_start();
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gen_io_start();
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ops->translate_insn(db, cpu);
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ops->translate_insn(db, cpu);
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@ -111,7 +110,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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/* Stop translation if the output buffer is full,
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/* Stop translation if the output buffer is full,
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or we have executed all of the allowed instructions. */
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or we have executed all of the allowed instructions. */
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if (tcg_op_buf_full() || db->num_insns >= max_insns) {
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if (tcg_op_buf_full() || db->num_insns >= db->max_insns) {
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db->is_jmp = DISAS_TOO_MANY;
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db->is_jmp = DISAS_TOO_MANY;
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break;
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break;
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}
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}
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@ -58,6 +58,7 @@ typedef enum DisasJumpType {
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* disassembly).
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* disassembly).
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* @is_jmp: What instruction to disassemble next.
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* @is_jmp: What instruction to disassemble next.
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* @num_insns: Number of translated instructions (including current).
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* @num_insns: Number of translated instructions (including current).
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* @max_insns: Maximum number of instructions to be translated in this TB.
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* @singlestep_enabled: "Hardware" single stepping enabled.
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* @singlestep_enabled: "Hardware" single stepping enabled.
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*
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*
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* Architecture-agnostic disassembly context.
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* Architecture-agnostic disassembly context.
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@ -67,7 +68,8 @@ typedef struct DisasContextBase {
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target_ulong pc_first;
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target_ulong pc_first;
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target_ulong pc_next;
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target_ulong pc_next;
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DisasJumpType is_jmp;
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DisasJumpType is_jmp;
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unsigned int num_insns;
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int num_insns;
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int max_insns;
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bool singlestep_enabled;
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bool singlestep_enabled;
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} DisasContextBase;
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} DisasContextBase;
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@ -76,7 +78,6 @@ typedef struct DisasContextBase {
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* @init_disas_context:
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* @init_disas_context:
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* Initialize the target-specific portions of DisasContext struct.
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* Initialize the target-specific portions of DisasContext struct.
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* The generic DisasContextBase has already been initialized.
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* The generic DisasContextBase has already been initialized.
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* Return max_insns, modified as necessary by db->tb->flags.
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*
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*
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* @tb_start:
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* @tb_start:
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* Emit any code required before the start of the main loop,
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* Emit any code required before the start of the main loop,
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@ -106,8 +107,7 @@ typedef struct DisasContextBase {
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* Print instruction disassembly to log.
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* Print instruction disassembly to log.
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*/
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*/
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typedef struct TranslatorOps {
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typedef struct TranslatorOps {
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int (*init_disas_context)(DisasContextBase *db, CPUState *cpu,
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void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
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int max_insns);
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void (*tb_start)(DisasContextBase *db, CPUState *cpu);
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void (*tb_start)(DisasContextBase *db, CPUState *cpu);
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void (*insn_start)(DisasContextBase *db, CPUState *cpu);
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void (*insn_start)(DisasContextBase *db, CPUState *cpu);
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bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu,
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bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu,
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@ -2919,8 +2919,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
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return ret;
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return ret;
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}
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}
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static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
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static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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CPUState *cpu, int max_insns)
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{
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUAlphaState *env = cpu->env_ptr;
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CPUAlphaState *env = cpu->env_ptr;
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@ -2959,8 +2958,7 @@ static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
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mask = TARGET_PAGE_MASK;
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mask = TARGET_PAGE_MASK;
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}
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}
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bound = -(ctx->base.pc_first | mask) / 4;
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bound = -(ctx->base.pc_first | mask) / 4;
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ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
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return MIN(max_insns, bound);
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}
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}
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static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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static void alpha_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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@ -13224,8 +13224,8 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
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free_tmp_a64(s);
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free_tmp_a64(s);
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}
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}
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static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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CPUState *cpu, int max_insns)
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CPUState *cpu)
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{
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUARMState *env = cpu->env_ptr;
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CPUARMState *env = cpu->env_ptr;
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@ -13288,11 +13288,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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if (dc->ss_active) {
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if (dc->ss_active) {
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bound = 1;
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bound = 1;
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}
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}
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max_insns = MIN(max_insns, bound);
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dc->base.max_insns = MIN(dc->base.max_insns, bound);
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init_tmp_a64_array(dc);
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init_tmp_a64_array(dc);
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return max_insns;
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}
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}
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static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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@ -12243,8 +12243,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
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return !thumb_insn_is_16bit(s, insn);
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return !thumb_insn_is_16bit(s, insn);
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}
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}
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static int arm_tr_init_disas_context(DisasContextBase *dcbase,
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static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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CPUState *cs, int max_insns)
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{
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUARMState *env = cs->env_ptr;
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CPUARMState *env = cs->env_ptr;
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@ -12305,14 +12304,14 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
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/* If architectural single step active, limit to 1. */
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/* If architectural single step active, limit to 1. */
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if (is_singlestepping(dc)) {
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if (is_singlestepping(dc)) {
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max_insns = 1;
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dc->base.max_insns = 1;
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}
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}
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/* ARM is a fixed-length ISA. Bound the number of insns to execute
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/* ARM is a fixed-length ISA. Bound the number of insns to execute
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to those left on the page. */
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to those left on the page. */
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if (!dc->thumb) {
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if (!dc->thumb) {
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int bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
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int bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
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max_insns = MIN(max_insns, bound);
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dc->base.max_insns = MIN(dc->base.max_insns, bound);
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}
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}
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cpu_F0s = tcg_temp_new_i32();
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cpu_F0s = tcg_temp_new_i32();
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@ -12323,8 +12322,6 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
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cpu_V1 = cpu_F1d;
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cpu_V1 = cpu_F1d;
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/* FIXME: cpu_M0 can probably be the same as cpu_V0. */
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/* FIXME: cpu_M0 can probably be the same as cpu_V0. */
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cpu_M0 = tcg_temp_new_i64();
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cpu_M0 = tcg_temp_new_i64();
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return max_insns;
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}
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}
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static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
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static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
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@ -4669,8 +4669,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
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return gen_illegal(ctx);
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return gen_illegal(ctx);
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}
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}
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static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
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static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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CPUState *cs, int max_insns)
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{
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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int bound;
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int bound;
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@ -4700,14 +4699,12 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
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/* Bound the number of instructions by those left on the page. */
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/* Bound the number of instructions by those left on the page. */
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bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
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bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
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bound = MIN(max_insns, bound);
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ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
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ctx->ntempr = 0;
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ctx->ntempr = 0;
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ctx->ntempl = 0;
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ctx->ntempl = 0;
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memset(ctx->tempr, 0, sizeof(ctx->tempr));
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memset(ctx->tempr, 0, sizeof(ctx->tempr));
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memset(ctx->templ, 0, sizeof(ctx->templ));
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memset(ctx->templ, 0, sizeof(ctx->templ));
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return bound;
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}
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}
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static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
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static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
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@ -8402,8 +8402,7 @@ void tcg_x86_init(void)
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}
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}
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}
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}
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static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
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static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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int max_insns)
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{
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUX86State *env = cpu->env_ptr;
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CPUX86State *env = cpu->env_ptr;
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@ -8470,8 +8469,6 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
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cpu_ptr0 = tcg_temp_new_ptr();
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cpu_ptr0 = tcg_temp_new_ptr();
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cpu_ptr1 = tcg_temp_new_ptr();
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cpu_ptr1 = tcg_temp_new_ptr();
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cpu_cc_srcT = tcg_temp_local_new();
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cpu_cc_srcT = tcg_temp_local_new();
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return max_insns;
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}
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}
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static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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@ -7215,8 +7215,7 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
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#endif
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#endif
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}
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}
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static int ppc_tr_init_disas_context(DisasContextBase *dcbase,
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static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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CPUState *cs, int max_insns)
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{
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPUPPCState *env = cs->env_ptr;
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CPUPPCState *env = cs->env_ptr;
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@ -7281,7 +7280,7 @@ static int ppc_tr_init_disas_context(DisasContextBase *dcbase,
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#endif
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#endif
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bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
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bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
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return MIN(max_insns, bound);
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ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
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}
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}
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static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
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static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
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