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Preliminary MIPS 64-bit MMU implementation, by Aurelien Jarno. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2794 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-05-09 09:34:30 +00:00
parent a6763a5881
commit b4ab4b4e1b
1 changed files with 57 additions and 5 deletions
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62
target-mips/helper.c
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@ -77,8 +77,13 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
int *prot, target_ulong address, int *prot, target_ulong address,
int rw, int access_type) int rw, int access_type)
{ {
/* User mode can only access useg */ /* User mode can only access useg/xuseg */
int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
#ifdef TARGET_MIPS64
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
#endif
int ret = TLBRET_MATCH; int ret = TLBRET_MATCH;
#if 0 #if 0
@ -87,10 +92,18 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
user_mode, env->hflags); user_mode, env->hflags);
} }
#endif #endif
#ifdef TARGET_MIPS64
if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
return TLBRET_BADADDR;
#else
if (user_mode && address > 0x7FFFFFFFUL) if (user_mode && address > 0x7FFFFFFFUL)
return TLBRET_BADADDR; return TLBRET_BADADDR;
if (address < (int32_t)0x80000000UL) { #endif
if (!(env->CP0_Status & (1 << CP0St_ERL))) {
if (address <= (int32_t)0x7FFFFFFFUL) {
/* useg */
if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) {
#ifdef MIPS_USES_R4K_TLB #ifdef MIPS_USES_R4K_TLB
ret = map_address(env, physical, prot, address, rw, access_type); ret = map_address(env, physical, prot, address, rw, access_type);
#else #else
@ -101,6 +114,45 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
*physical = address; *physical = address;
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
} }
#ifdef TARGET_MIPS64
/*
XXX: Assuming :
- PABITS = 36 (correct for MIPS64R1)
- SEGBITS = 40
*/
} else if (address < 0x3FFFFFFFFFFFFFFFULL) {
/* xuseg */
if (UX && address < 0x000000FFFFFFFFFFULL) {
ret = map_address(env, physical, prot, address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
} else if (address < 0x7FFFFFFFFFFFFFFFULL) {
/* xsseg */
if (SX && address < 0x400000FFFFFFFFFFULL) {
ret = map_address(env, physical, prot, address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
} else if (address < 0xBFFFFFFFFFFFFFFFULL) {
/* xkphys */
/* XXX: check supervisor mode */
if (KX && (address & 0x03FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
{
*physical = address & 0X000000FFFFFFFFFFULL;
*prot = PAGE_READ | PAGE_WRITE;
} else {
ret = TLBRET_BADADDR;
}
} else if (address < 0xFFFFFFFF7FFFFFFFULL) {
/* xkseg */
/* XXX: check supervisor mode */
if (KX && address < 0xC00000FF7FFFFFFFULL) {
ret = map_address(env, physical, prot, address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
#endif
} else if (address < (int32_t)0xA0000000UL) { } else if (address < (int32_t)0xA0000000UL) {
/* kseg0 */ /* kseg0 */
/* XXX: check supervisor mode */ /* XXX: check supervisor mode */
@ -116,7 +168,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
#ifdef MIPS_USES_R4K_TLB #ifdef MIPS_USES_R4K_TLB
ret = map_address(env, physical, prot, address, rw, access_type); ret = map_address(env, physical, prot, address, rw, access_type);
#else #else
*physical = address; *physical = address & 0xFFFFFFFF;
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
#endif #endif
} else { } else {
@ -126,7 +178,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
#ifdef MIPS_USES_R4K_TLB #ifdef MIPS_USES_R4K_TLB
ret = map_address(env, physical, prot, address, rw, access_type); ret = map_address(env, physical, prot, address, rw, access_type);
#else #else
*physical = address; *physical = address & 0xFFFFFFFF;
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
#endif #endif
} }