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target-xtensa: add DEBUGCAUSE SR and configuration 

DEBUGCAUSE SR holds information about the most recent debug exception.
See ISA, 4.7.7 for more details.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2011-12-14 02:13:40 +04:00
parent a044ec2a06
commit ab58c5b4fd
2 changed files with 21 additions and 0 deletions
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15
target-xtensa/cpu.h
View File

@ -137,6 +137,7 @@ enum {
PS = 230, PS = 230,
VECBASE = 231, VECBASE = 231,
EXCCAUSE = 232, EXCCAUSE = 232,
DEBUGCAUSE = 233,
CCOUNT = 234, CCOUNT = 234,
PRID = 235, PRID = 235,
EXCVADDR = 238, EXCVADDR = 238,
@ -161,6 +162,15 @@ enum {
#define PS_WOE 0x40000 #define PS_WOE 0x40000
#define DEBUGCAUSE_IC 0x1
#define DEBUGCAUSE_IB 0x2
#define DEBUGCAUSE_DB 0x4
#define DEBUGCAUSE_BI 0x8
#define DEBUGCAUSE_BN 0x10
#define DEBUGCAUSE_DI 0x20
#define DEBUGCAUSE_DBNUM 0xf00
#define DEBUGCAUSE_DBNUM_SHIFT 8
#define MAX_NAREG 64 #define MAX_NAREG 64
#define MAX_NINTERRUPT 32 #define MAX_NINTERRUPT 32
#define MAX_NLEVEL 6 #define MAX_NLEVEL 6
@ -279,6 +289,11 @@ typedef struct XtensaConfig {
uint32_t timerint[MAX_NCCOMPARE]; uint32_t timerint[MAX_NCCOMPARE];
unsigned nextint; unsigned nextint;
unsigned extint[MAX_NINTERRUPT]; unsigned extint[MAX_NINTERRUPT];
unsigned debug_level;
unsigned nibreak;
unsigned ndbreak;
uint32_t clock_freq_khz; uint32_t clock_freq_khz;
xtensa_tlb itlb; xtensa_tlb itlb;

6
target-xtensa/translate.c
View File

@ -119,6 +119,7 @@ static const char * const sregnames[256] = {
[PS] = "PS", [PS] = "PS",
[VECBASE] = "VECBASE", [VECBASE] = "VECBASE",
[EXCCAUSE] = "EXCCAUSE", [EXCCAUSE] = "EXCCAUSE",
[DEBUGCAUSE] = "DEBUGCAUSE",
[CCOUNT] = "CCOUNT", [CCOUNT] = "CCOUNT",
[PRID] = "PRID", [PRID] = "PRID",
[EXCVADDR] = "EXCVADDR", [EXCVADDR] = "EXCVADDR",
@ -535,6 +536,10 @@ static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
gen_jumpi_check_loop_end(dc, -1); gen_jumpi_check_loop_end(dc, -1);
} }
static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
}
static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v) static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{ {
} }
@ -571,6 +576,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
[INTCLEAR] = gen_wsr_intclear, [INTCLEAR] = gen_wsr_intclear,
[INTENABLE] = gen_wsr_intenable, [INTENABLE] = gen_wsr_intenable,
[PS] = gen_wsr_ps, [PS] = gen_wsr_ps,
[DEBUGCAUSE] = gen_wsr_debugcause,
[PRID] = gen_wsr_prid, [PRID] = gen_wsr_prid,
[CCOMPARE] = gen_wsr_ccompare, [CCOMPARE] = gen_wsr_ccompare,
[CCOMPARE + 1] = gen_wsr_ccompare, [CCOMPARE + 1] = gen_wsr_ccompare,