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target-arm: Simplify three-register pairwise code 

Since we know that the case of (pairwise && q) has been caught
earlier, we can simplify the register setup code for each pass
in the three-register-same-size Neon loop.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Juha Riihimäki 2011-04-11 16:26:13 +01:00 committed by Aurelien Jarno
parent 25f84f7948
commit a5a14945da
1 changed files with 8 additions and 11 deletions
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19
target-arm/translate.c
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@ -4328,7 +4328,6 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
int count; int count;
int pairwise; int pairwise;
int u; int u;
int n;
uint32_t imm, mask; uint32_t imm, mask;
TCGv tmp, tmp2, tmp3, tmp4, tmp5; TCGv tmp, tmp2, tmp3, tmp4, tmp5;
TCGv_i64 tmp64; TCGv_i64 tmp64;
@ -4480,16 +4479,12 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
if (pairwise) { if (pairwise) {
/* Pairwise. */ /* Pairwise. */
if (q) if (pass < 1) {
n = (pass & 1) * 2; tmp = neon_load_reg(rn, 0);
else tmp2 = neon_load_reg(rn, 1);
n = 0;
if (pass < q + 1) {
tmp = neon_load_reg(rn, n);
tmp2 = neon_load_reg(rn, n + 1);
} else { } else {
tmp = neon_load_reg(rm, n); tmp = neon_load_reg(rm, 0);
tmp2 = neon_load_reg(rm, n + 1); tmp2 = neon_load_reg(rm, 1);
} }
} else { } else {
/* Elementwise. */ /* Elementwise. */
@ -5147,6 +5142,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
/* VMOV, VMVN. */ /* VMOV, VMVN. */
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
if (op == 14 && invert) { if (op == 14 && invert) {
int n;
uint32_t val; uint32_t val;
val = 0; val = 0;
for (n = 0; n < 4; n++) { for (n = 0; n < 4; n++) {
@ -5575,6 +5571,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
break; break;
case 33: /* VTRN */ case 33: /* VTRN */
if (size == 2) { if (size == 2) {
int n;
for (n = 0; n < (q ? 4 : 2); n += 2) { for (n = 0; n < (q ? 4 : 2); n += 2) {
tmp = neon_load_reg(rm, n); tmp = neon_load_reg(rm, n);
tmp2 = neon_load_reg(rd, n + 1); tmp2 = neon_load_reg(rd, n + 1);
@ -5866,7 +5863,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
} }
} else if ((insn & (1 << 10)) == 0) { } else if ((insn & (1 << 10)) == 0) {
/* VTBL, VTBX. */ /* VTBL, VTBX. */
n = ((insn >> 5) & 0x18) + 8; int n = ((insn >> 5) & 0x18) + 8;
if (insn & (1 << 6)) { if (insn & (1 << 6)) {
tmp = neon_load_reg(rd, 0); tmp = neon_load_reg(rd, 0);
} else { } else {