mirror of https://github.com/xqemu/xqemu.git
TCG/HPPA: use TCG_REG_CALL_STACK instead of TCG_REG_SP
Use TCG_REG_CALL_STACK instead of TCG_REG_SP for consistency. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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20be39de59
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a42bceec09
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@ -646,14 +646,14 @@ static void tcg_out_xmpyu(TCGContext *s, int retl, int reth,
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int arg1, int arg2)
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int arg1, int arg2)
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{
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{
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/* Store both words into the stack for copy to the FPU. */
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/* Store both words into the stack for copy to the FPU. */
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tcg_out_ldst(s, arg1, TCG_REG_SP, STACK_TEMP_OFS, INSN_STW);
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tcg_out_ldst(s, arg1, TCG_REG_CALL_STACK, STACK_TEMP_OFS, INSN_STW);
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tcg_out_ldst(s, arg2, TCG_REG_SP, STACK_TEMP_OFS + 4, INSN_STW);
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tcg_out_ldst(s, arg2, TCG_REG_CALL_STACK, STACK_TEMP_OFS + 4, INSN_STW);
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/* Load both words into the FPU at the same time. We get away
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/* Load both words into the FPU at the same time. We get away
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with this because we can address the left and right half of the
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with this because we can address the left and right half of the
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FPU registers individually once loaded. */
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FPU registers individually once loaded. */
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/* fldds stack_temp(sp),fr22 */
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/* fldds stack_temp(sp),fr22 */
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tcg_out32(s, INSN_FLDDS | INSN_R2(TCG_REG_SP)
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tcg_out32(s, INSN_FLDDS | INSN_R2(TCG_REG_CALL_STACK)
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| INSN_IM5(STACK_TEMP_OFS) | INSN_T(22));
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| INSN_IM5(STACK_TEMP_OFS) | INSN_T(22));
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/* xmpyu fr22r,fr22,fr22 */
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/* xmpyu fr22r,fr22,fr22 */
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@ -661,15 +661,16 @@ static void tcg_out_xmpyu(TCGContext *s, int retl, int reth,
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/* Store the 64-bit result back into the stack. */
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/* Store the 64-bit result back into the stack. */
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/* fstds stack_temp(sp),fr22 */
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/* fstds stack_temp(sp),fr22 */
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tcg_out32(s, INSN_FSTDS | INSN_R2(TCG_REG_SP)
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tcg_out32(s, INSN_FSTDS | INSN_R2(TCG_REG_CALL_STACK)
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| INSN_IM5(STACK_TEMP_OFS) | INSN_T(22));
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| INSN_IM5(STACK_TEMP_OFS) | INSN_T(22));
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/* Load the pieces of the result that the caller requested. */
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/* Load the pieces of the result that the caller requested. */
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if (reth) {
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if (reth) {
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tcg_out_ldst(s, reth, TCG_REG_SP, STACK_TEMP_OFS, INSN_LDW);
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tcg_out_ldst(s, reth, TCG_REG_CALL_STACK, STACK_TEMP_OFS, INSN_LDW);
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}
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}
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if (retl) {
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if (retl) {
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tcg_out_ldst(s, retl, TCG_REG_SP, STACK_TEMP_OFS + 4, INSN_LDW);
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tcg_out_ldst(s, retl, TCG_REG_CALL_STACK, STACK_TEMP_OFS + 4,
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INSN_LDW);
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}
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}
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}
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}
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@ -1198,7 +1199,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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}
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}
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tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R23, datahi_reg);
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tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R23, datahi_reg);
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tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R24, datalo_reg);
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tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R24, datalo_reg);
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tcg_out_st(s, TCG_TYPE_I32, argreg, TCG_REG_SP,
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tcg_out_st(s, TCG_TYPE_I32, argreg, TCG_REG_CALL_STACK,
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TCG_TARGET_CALL_STACK_OFFSET - 4);
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TCG_TARGET_CALL_STACK_OFFSET - 4);
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break;
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break;
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default:
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default:
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@ -1616,16 +1617,16 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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& -TCG_TARGET_STACK_ALIGN);
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& -TCG_TARGET_STACK_ALIGN);
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/* The return address is stored in the caller's frame. */
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/* The return address is stored in the caller's frame. */
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tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_RP, TCG_REG_SP, -20);
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tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_RP, TCG_REG_CALL_STACK, -20);
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/* Allocate stack frame, saving the first register at the same time. */
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/* Allocate stack frame, saving the first register at the same time. */
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tcg_out_ldst(s, tcg_target_callee_save_regs[0],
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tcg_out_ldst(s, tcg_target_callee_save_regs[0],
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TCG_REG_SP, frame_size, INSN_STWM);
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TCG_REG_CALL_STACK, frame_size, INSN_STWM);
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/* Save all callee saved registers. */
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/* Save all callee saved registers. */
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for (i = 1; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
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for (i = 1; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
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tcg_out_st(s, TCG_TYPE_PTR, tcg_target_callee_save_regs[i],
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tcg_out_st(s, TCG_TYPE_PTR, tcg_target_callee_save_regs[i],
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TCG_REG_SP, -frame_size + i * 4);
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TCG_REG_CALL_STACK, -frame_size + i * 4);
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}
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}
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#ifdef CONFIG_USE_GUEST_BASE
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#ifdef CONFIG_USE_GUEST_BASE
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@ -1642,16 +1643,17 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R18, TCG_REG_R31);
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tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R18, TCG_REG_R31);
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/* Restore callee saved registers. */
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/* Restore callee saved registers. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_RP, TCG_REG_SP, -frame_size - 20);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_RP, TCG_REG_CALL_STACK,
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-frame_size - 20);
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for (i = 1; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
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for (i = 1; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
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tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_callee_save_regs[i],
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tcg_out_ld(s, TCG_TYPE_PTR, tcg_target_callee_save_regs[i],
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TCG_REG_SP, -frame_size + i * 4);
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TCG_REG_CALL_STACK, -frame_size + i * 4);
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}
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}
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/* Deallocate stack frame and return. */
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/* Deallocate stack frame and return. */
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tcg_out32(s, INSN_BV | INSN_R2(TCG_REG_RP));
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tcg_out32(s, INSN_BV | INSN_R2(TCG_REG_RP));
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tcg_out_ldst(s, tcg_target_callee_save_regs[0],
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tcg_out_ldst(s, tcg_target_callee_save_regs[0],
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TCG_REG_SP, -frame_size, INSN_LDWM);
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TCG_REG_CALL_STACK, -frame_size, INSN_LDWM);
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}
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}
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static void tcg_target_init(TCGContext *s)
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static void tcg_target_init(TCGContext *s)
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@ -1678,7 +1680,7 @@ static void tcg_target_init(TCGContext *s)
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R19); /* clobbered w/o pic */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R19); /* clobbered w/o pic */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R20); /* reserved */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R20); /* reserved */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_DP); /* data pointer */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_DP); /* data pointer */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); /* stack pointer */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R31); /* ble link reg */
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_R31); /* ble link reg */
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tcg_add_target_add_op_defs(hppa_op_defs);
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tcg_add_target_add_op_defs(hppa_op_defs);
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