mirror of https://github.com/xqemu/xqemu.git
CRIS: Remove some old dyngen T0/T1 fiddle. More usage of the results from the x flag liveness analysis.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4433 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
34808ac170
commit
a39f8f3ad9
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@ -483,24 +483,36 @@ static inline void t_gen_addx_carry(TCGv d)
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tcg_gen_discard_tl(c);
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}
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static inline void t_gen_subx_carry(TCGv d)
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static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
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{
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TCGv x, c;
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if (dc->flagx_live) {
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TCGv x, c;
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x = tcg_temp_new(TCG_TYPE_TL);
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c = tcg_temp_new(TCG_TYPE_TL);
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t_gen_mov_TN_preg(x, PR_CCS);
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tcg_gen_mov_tl(c, x);
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x = tcg_temp_new(TCG_TYPE_TL);
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c = tcg_temp_new(TCG_TYPE_TL);
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t_gen_mov_TN_preg(x, PR_CCS);
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tcg_gen_mov_tl(c, x);
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/* Propagate carry into d if X is set. Branch free. */
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tcg_gen_andi_tl(c, c, C_FLAG);
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tcg_gen_andi_tl(x, x, X_FLAG);
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tcg_gen_shri_tl(x, x, 4);
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/* Propagate carry into d if X is set. Branch free. */
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tcg_gen_andi_tl(c, c, C_FLAG);
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tcg_gen_andi_tl(x, x, X_FLAG);
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tcg_gen_shri_tl(x, x, 4);
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tcg_gen_and_tl(x, x, c);
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tcg_gen_sub_tl(d, d, x);
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tcg_gen_discard_tl(x);
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tcg_gen_discard_tl(c);
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tcg_gen_and_tl(x, x, c);
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tcg_gen_sub_tl(d, d, x);
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tcg_gen_discard_tl(x);
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tcg_gen_discard_tl(c);
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} else {
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if (dc->flags_x) {
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TCGv c;
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c = tcg_temp_new(TCG_TYPE_TL);
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/* C flag is already at bit 0. */
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tcg_gen_andi_tl(c, c, C_FLAG);
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tcg_gen_add_tl(d, d, c);
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tcg_gen_discard_tl(c);
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}
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}
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}
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/* Swap the two bytes within each half word of the s operand.
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@ -633,7 +645,7 @@ static inline void cris_clear_x_flag(DisasContext *dc)
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{
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if (!dc->flagx_live
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|| (dc->flagx_live && dc->flags_x)
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|| dc->cc_op != CC_OP_FLAGS)
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|| dc->cc_op == CC_OP_FLAGS)
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tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
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dc->flagx_live = 1;
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dc->flags_x = 0;
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@ -760,7 +772,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
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/* Extended arithmetics. */
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t_gen_subx_carry(cpu_T[0]);
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t_gen_subx_carry(dc, cpu_T[0]);
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break;
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case CC_OP_MOVE:
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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@ -786,7 +798,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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case CC_OP_NEG:
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tcg_gen_neg_tl(cpu_T[0], cpu_T[1]);
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/* Extended arithmetics. */
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t_gen_subx_carry(cpu_T[0]);
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t_gen_subx_carry(dc, cpu_T[0]);
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break;
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case CC_OP_LZ:
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t_gen_lz_i32(cpu_T[0], cpu_T[1]);
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@ -827,15 +839,12 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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}
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break;
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case CC_OP_CMP:
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tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
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tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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/* CRIS flag evaluation needs ~src. */
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tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
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/* CRIS flag evaluation needs ~src. */
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tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
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tcg_gen_xori_tl(cpu_T[1], cpu_T[1], ~0);
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/* Extended arithmetics. */
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t_gen_subx_carry(cpu_T[0]);
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t_gen_subx_carry(dc, cpu_T[0]);
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writeback = 0;
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break;
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default:
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@ -855,17 +864,13 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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/* Writeback. */
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if (writeback) {
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if (size == 4)
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t_gen_mov_reg_TN(rd, cpu_T[0]);
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tcg_gen_mov_tl(cpu_R[rd], cpu_T[0]);
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else {
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tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
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t_gen_mov_TN_reg(cpu_T[0], rd);
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if (size == 1)
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
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tcg_gen_andi_tl(cpu_R[rd], cpu_R[rd], ~0xff);
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else
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
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tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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t_gen_mov_reg_TN(rd, cpu_T[0]);
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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tcg_gen_andi_tl(cpu_R[rd], cpu_R[rd], ~0xffff);
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tcg_gen_or_tl(cpu_R[rd], cpu_R[rd], cpu_T[0]);
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}
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}
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if (dc->update_cc)
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@ -1208,7 +1213,6 @@ static inline void do_postinc (DisasContext *dc, int size)
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tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
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}
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static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
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int size, int s_ext)
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{
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@ -1352,7 +1356,7 @@ static unsigned int dec_moveq(DisasContext *dc)
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imm = sign_extend(dc->op1, 5);
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DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
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t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
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tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
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return 2;
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}
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static unsigned int dec_subq(DisasContext *dc)
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@ -1363,7 +1367,7 @@ static unsigned int dec_subq(DisasContext *dc)
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cris_cc_mask(dc, CC_MASK_NZVC);
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/* Fetch register operand, */
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t_gen_mov_TN_reg(cpu_T[0], dc->op2);
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tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
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tcg_gen_movi_tl(cpu_T[1], dc->op1);
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crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
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return 2;
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