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tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation. 

The test TCG_TARGET_REG_BITS==64 is exactly the feature that we
are checking for, whereas something involving __sparc_v9__ or
__sparc_v8plus__ should be reserved for something ISA related,
as with SMULX.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2009-12-17 23:47:54 -08:00 committed by Blue Swirl
parent 431722077a
commit a212ea7553
1 changed files with 16 additions and 16 deletions
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32
tcg/sparc/tcg-target.c
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@ -348,13 +348,13 @@ static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
{ {
if (!check_fit_tl(arg, 10)) if (!check_fit_tl(arg, 10))
tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL); tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) if (TCG_TARGET_REG_BITS == 64) {
tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
INSN_IMM13(arg & 0x3ff)); INSN_IMM13(arg & 0x3ff));
#else } else {
tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
INSN_IMM13(arg & 0x3ff)); INSN_IMM13(arg & 0x3ff));
#endif }
} }
static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
@ -447,7 +447,7 @@ static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
} }
} }
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index) static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
{ {
int32_t val; int32_t val;
@ -493,7 +493,7 @@ static void tcg_out_brcond_i32(TCGContext *s, int cond,
tcg_out_nop(s); tcg_out_nop(s);
} }
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
static void tcg_out_brcond_i64(TCGContext *s, int cond, static void tcg_out_brcond_i64(TCGContext *s, int cond,
TCGArg arg1, TCGArg arg2, int const_arg2, TCGArg arg1, TCGArg arg2, int const_arg2,
int label_index) int label_index)
@ -989,7 +989,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
break; break;
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
#define OP_32_64(x) \ #define OP_32_64(x) \
glue(glue(case INDEX_op_, x), _i32:) \ glue(glue(case INDEX_op_, x), _i32:) \
glue(glue(case INDEX_op_, x), _i64:) glue(glue(case INDEX_op_, x), _i64:)
@ -1010,7 +1010,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out_ldst(s, args[0], args[1], args[2], LDSH); tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
break; break;
case INDEX_op_ld_i32: case INDEX_op_ld_i32:
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
case INDEX_op_ld32u_i64: case INDEX_op_ld32u_i64:
#endif #endif
tcg_out_ldst(s, args[0], args[1], args[2], LDUW); tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
@ -1022,7 +1022,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out_ldst(s, args[0], args[1], args[2], STH); tcg_out_ldst(s, args[0], args[1], args[2], STH);
break; break;
case INDEX_op_st_i32: case INDEX_op_st_i32:
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
case INDEX_op_st32_i64: case INDEX_op_st32_i64:
#endif #endif
tcg_out_ldst(s, args[0], args[1], args[2], STW); tcg_out_ldst(s, args[0], args[1], args[2], STW);
@ -1106,7 +1106,7 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
tcg_out_qemu_st(s, args, 2); tcg_out_qemu_st(s, args, 2);
break; break;
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
case INDEX_op_movi_i64: case INDEX_op_movi_i64:
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
break; break;
@ -1208,7 +1208,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_qemu_st16, { "L", "L" } }, { INDEX_op_qemu_st16, { "L", "L" } },
{ INDEX_op_qemu_st32, { "L", "L" } }, { INDEX_op_qemu_st32, { "L", "L" } },
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
{ INDEX_op_mov_i64, { "r", "r" } }, { INDEX_op_mov_i64, { "r", "r" } },
{ INDEX_op_movi_i64, { "r" } }, { INDEX_op_movi_i64, { "r" } },
{ INDEX_op_ld8u_i64, { "r", "r" } }, { INDEX_op_ld8u_i64, { "r", "r" } },
@ -1246,7 +1246,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
void tcg_target_init(TCGContext *s) void tcg_target_init(TCGContext *s)
{ {
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
#endif #endif
tcg_regset_set32(tcg_target_call_clobber_regs, 0, tcg_regset_set32(tcg_target_call_clobber_regs, 0,
@ -1267,7 +1267,7 @@ void tcg_target_init(TCGContext *s)
tcg_regset_clear(s->reserved_regs); tcg_regset_clear(s->reserved_regs);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__) #if TCG_TARGET_REG_BITS == 64
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
#endif #endif
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use