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pci: remove hard-coded bar size in msix_init_exclusive_bar() 

This patch lets msix_init_exclusive_bar() can calculate the bar and
pba size based on the number of MSI-X vectors other than using a
hard-coded limit 4096. This is needed to allow device to have more
than 128 MSI_X vectors. To keep migration compatibility, keep using
4096 as bar size and 2048 for pba offset.

Notes: We don't care about the case that using vectors > 128 for
legacy machine type. Since we limit the queue max to 64, so vectors >=
65 is meaningless.

Virtio device will be the first user for this.

Cc: Keith Busch <keith.busch@intel.com>
Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jason Wang 2015-04-23 14:21:49 +08:00 committed by Michael S. Tsirkin
parent 851c2a75a6
commit a0ccd2123e
1 changed files with 19 additions and 11 deletions
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30
hw/pci/msix.c
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@ -295,29 +295,37 @@ int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
{ {
int ret; int ret;
char *name; char *name;
uint32_t bar_size = 4096;
uint32_t bar_pba_offset = bar_size / 2;
uint32_t bar_pba_size = (nentries / 8 + 1) * 8;
/* /*
* Migration compatibility dictates that this remains a 4k * Migration compatibility dictates that this remains a 4k
* BAR with the vector table in the lower half and PBA in * BAR with the vector table in the lower half and PBA in
* the upper half. Do not use these elsewhere! * the upper half for nentries which is lower or equal to 128.
* No need to care about using more than 65 entries for legacy
* machine types who has at most 64 queues.
*/ */
#define MSIX_EXCLUSIVE_BAR_SIZE 4096 if (nentries * PCI_MSIX_ENTRY_SIZE > bar_pba_offset) {
#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0 bar_pba_offset = nentries * PCI_MSIX_ENTRY_SIZE;
#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2) }
#define MSIX_EXCLUSIVE_CAP_OFFSET 0
if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) { if (bar_pba_offset + bar_pba_size > 4096) {
return -EINVAL; bar_size = bar_pba_offset + bar_pba_size;
}
if (bar_size & (bar_size - 1)) {
bar_size = 1 << qemu_fls(bar_size);
} }
name = g_strdup_printf("%s-msix", dev->name); name = g_strdup_printf("%s-msix", dev->name);
memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, MSIX_EXCLUSIVE_BAR_SIZE); memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, bar_size);
g_free(name); g_free(name);
ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr, ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar, 0, &dev->msix_exclusive_bar,
bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET, bar_nr, bar_pba_offset,
MSIX_EXCLUSIVE_CAP_OFFSET); 0);
if (ret) { if (ret) {
return ret; return ret;
} }