mirror of https://github.com/xqemu/xqemu.git
Queued tcg patches
-----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJZ/CrmAAoJEGTfOOivfiFfUP4IALDxb3kXUGYELNfQR8+P1Bnk x4p5dbDCfyIvMFGIngbjaCYlv/sMIcY780yQLZN0W+hUfr7//2kRemzNPoGWpY1p w/tsKzKn/EIpXoKruD12q5qUL6ceIabwuUdDQ5Ezc4tTAz/Nd1kiMA1IA+7i3Gfb E9F/0LbG+wXSTD87A7T754dsSLSszL0RaFwx6nJYxk876CjKv9mjJAPlmA23PKTa W8Qsk4+Ou5mP0/jyxBEQ4KAgY+LE2maP///diPuZKy7iQbhWwogga7VX1ek/o+4T 74J1ye/5SSeISGJpIW18PmR0Vcf44eqz1aMavvFRwIw8Wr6bHQ9mcQlpakWjuWo= =ncG6 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20171103' into staging Queued tcg patches # gpg: Signature made Fri 03 Nov 2017 08:37:58 GMT # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20171103: cpu-exec: Exit exclusive region on longjmp from step_atomic tcg/s390x: Use constant pool for prologue tcg: Allow constant pool entries in the prologue Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
9c4da1fa2b
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@ -233,6 +233,8 @@ void cpu_exec_step_atomic(CPUState *cpu)
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uint32_t flags;
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uint32_t cflags = 1;
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uint32_t cf_mask = cflags & CF_HASH_MASK;
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/* volatile because we modify it between setjmp and longjmp */
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volatile bool in_exclusive_region = false;
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if (sigsetjmp(cpu->jmp_env, 0) == 0) {
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tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
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@ -251,14 +253,12 @@ void cpu_exec_step_atomic(CPUState *cpu)
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/* Since we got here, we know that parallel_cpus must be true. */
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parallel_cpus = false;
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in_exclusive_region = true;
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cc->cpu_exec_enter(cpu);
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/* execute the generated code */
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trace_exec_tb(tb, pc);
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cpu_tb_exec(cpu, tb);
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cc->cpu_exec_exit(cpu);
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parallel_cpus = true;
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end_exclusive();
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} else {
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/* We may have exited due to another problem here, so we need
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* to reset any tb_locks we may have taken but didn't release.
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@ -270,6 +270,15 @@ void cpu_exec_step_atomic(CPUState *cpu)
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#endif
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tb_lock_reset();
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}
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if (in_exclusive_region) {
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/* We might longjump out of either the codegen or the
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* execution, so must make sure we only end the exclusive
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* region if we started it.
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*/
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parallel_cpus = true;
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end_exclusive();
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}
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}
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struct tb_desc {
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@ -555,9 +555,6 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
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static const S390Opcode lli_insns[4] = {
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RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
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};
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static const S390Opcode ii_insns[4] = {
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RI_IILL, RI_IILH, RI_IIHL, RI_IIHH
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};
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static bool maybe_out_small_movi(TCGContext *s, TCGType type,
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TCGReg ret, tcg_target_long sval)
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@ -647,36 +644,19 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
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return;
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}
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/* When allowed, stuff it in the constant pool. */
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if (!in_prologue) {
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if (USE_REG_TB) {
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tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
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new_pool_label(s, sval, R_390_20, s->code_ptr - 2,
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-(intptr_t)s->code_gen_ptr);
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} else {
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tcg_out_insn(s, RIL, LGRL, ret, 0);
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new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
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}
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return;
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}
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/* What's left is for the prologue, loading GUEST_BASE, and because
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it failed to match above, is known to be a full 64-bit quantity.
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We could try more than this, but it probably wouldn't pay off. */
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if (s390_facilities & FACILITY_EXT_IMM) {
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tcg_out_insn(s, RIL, LLILF, ret, uval);
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tcg_out_insn(s, RIL, IIHF, ret, uval >> 32);
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/* Otherwise, stuff it in the constant pool. */
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if (s390_facilities & FACILITY_GEN_INST_EXT) {
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tcg_out_insn(s, RIL, LGRL, ret, 0);
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new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
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} else if (USE_REG_TB && !in_prologue) {
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tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
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new_pool_label(s, sval, R_390_20, s->code_ptr - 2,
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-(intptr_t)s->code_gen_ptr);
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} else {
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const S390Opcode *insns = lli_insns;
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int i;
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for (i = 0; i < 4; i++) {
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uint16_t part = uval >> (16 * i);
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if (part) {
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tcg_out_insn_RI(s, insns[i], ret, part);
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insns = ii_insns;
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}
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}
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TCGReg base = ret ? ret : TCG_TMP0;
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tcg_out_insn(s, RIL, LARL, base, 0);
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new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
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tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0);
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}
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}
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49
tcg/tcg.c
49
tcg/tcg.c
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@ -771,12 +771,32 @@ void tcg_prologue_init(TCGContext *s)
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/* Put the prologue at the beginning of code_gen_buffer. */
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buf0 = s->code_gen_buffer;
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total_size = s->code_gen_buffer_size;
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s->code_ptr = buf0;
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s->code_buf = buf0;
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s->data_gen_ptr = NULL;
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s->code_gen_prologue = buf0;
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/* Compute a high-water mark, at which we voluntarily flush the buffer
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and start over. The size here is arbitrary, significantly larger
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than we expect the code generation for any one opcode to require. */
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s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER);
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#ifdef TCG_TARGET_NEED_POOL_LABELS
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s->pool_labels = NULL;
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#endif
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/* Generate the prologue. */
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tcg_target_qemu_prologue(s);
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#ifdef TCG_TARGET_NEED_POOL_LABELS
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/* Allow the prologue to put e.g. guest_base into a pool entry. */
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{
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bool ok = tcg_out_pool_finalize(s);
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tcg_debug_assert(ok);
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}
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#endif
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buf1 = s->code_ptr;
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flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1);
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@ -785,21 +805,36 @@ void tcg_prologue_init(TCGContext *s)
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s->code_gen_ptr = buf1;
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s->code_gen_buffer = buf1;
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s->code_buf = buf1;
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total_size = s->code_gen_buffer_size - prologue_size;
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total_size -= prologue_size;
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s->code_gen_buffer_size = total_size;
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/* Compute a high-water mark, at which we voluntarily flush the buffer
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and start over. The size here is arbitrary, significantly larger
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than we expect the code generation for any one opcode to require. */
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s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER);
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tcg_register_jit(s->code_gen_buffer, total_size);
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#ifdef DEBUG_DISAS
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if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
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qemu_log_lock();
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qemu_log("PROLOGUE: [size=%zu]\n", prologue_size);
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log_disas(buf0, prologue_size);
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if (s->data_gen_ptr) {
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size_t code_size = s->data_gen_ptr - buf0;
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size_t data_size = prologue_size - code_size;
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size_t i;
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log_disas(buf0, code_size);
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for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) {
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if (sizeof(tcg_target_ulong) == 8) {
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qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n",
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(uintptr_t)s->data_gen_ptr + i,
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*(uint64_t *)(s->data_gen_ptr + i));
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} else {
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qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n",
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(uintptr_t)s->data_gen_ptr + i,
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*(uint32_t *)(s->data_gen_ptr + i));
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}
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}
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} else {
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log_disas(buf0, prologue_size);
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}
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qemu_log("\n");
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qemu_log_flush();
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qemu_log_unlock();
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