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target-arm: Handle UNDEFs for Neon single element load/stores 

Handle the UNDEF and UNPREDICTABLE cases for Neon "single element to
one lane" VLD and "single element from one lane" VST.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell 2011-04-18 19:07:11 +01:00 committed by Aurelien Jarno
parent dbf352ad6e
commit 93262b1625
1 changed files with 34 additions and 0 deletions
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34
target-arm/translate.c
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@ -3975,6 +3975,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
stride = (1 << size) * nregs; stride = (1 << size) * nregs;
} else { } else {
/* Single element. */ /* Single element. */
int idx = (insn >> 4) & 0xf;
pass = (insn >> 7) & 1; pass = (insn >> 7) & 1;
switch (size) { switch (size) {
case 0: case 0:
@ -3993,6 +3994,39 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
abort(); abort();
} }
nregs = ((insn >> 8) & 3) + 1; nregs = ((insn >> 8) & 3) + 1;
/* Catch the UNDEF cases. This is unavoidably a bit messy. */
switch (nregs) {
case 1:
if (((idx & (1 << size)) != 0) ||
(size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) {
return 1;
}
break;
case 3:
if ((idx & 1) != 0) {
return 1;
}
/* fall through */
case 2:
if (size == 2 && (idx & 2) != 0) {
return 1;
}
break;
case 4:
if ((size == 2) && ((idx & 3) == 3)) {
return 1;
}
break;
default:
abort();
}
if ((rd + stride * (nregs - 1)) > 31) {
/* Attempts to write off the end of the register file
* are UNPREDICTABLE; we choose to UNDEF because otherwise
* the neon_load_reg() would write off the end of the array.
*/
return 1;
}
addr = tcg_temp_new_i32(); addr = tcg_temp_new_i32();
load_reg_var(s, addr, rn); load_reg_var(s, addr, rn);
for (reg = 0; reg < nregs; reg++) { for (reg = 0; reg < nregs; reg++) {