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slavio_intctl: convert slaves interrupt controllers to memory API 

Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Benoît Canet 2011-11-15 12:14:00 +01:00 committed by Avi Kivity
parent 13c89a1125
commit 8bb5ef333a
1 changed files with 18 additions and 18 deletions
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36
hw/slavio_intctl.c
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@ -46,6 +46,7 @@
struct SLAVIO_INTCTLState; struct SLAVIO_INTCTLState;
typedef struct SLAVIO_CPUINTCTLState { typedef struct SLAVIO_CPUINTCTLState {
MemoryRegion iomem;
struct SLAVIO_INTCTLState *master; struct SLAVIO_INTCTLState *master;
uint32_t intreg_pending; uint32_t intreg_pending;
uint32_t cpu; uint32_t cpu;
@ -77,7 +78,8 @@ typedef struct SLAVIO_INTCTLState {
static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs); static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
// per-cpu interrupt controller // per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr) static uint64_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
SLAVIO_CPUINTCTLState *s = opaque; SLAVIO_CPUINTCTLState *s = opaque;
uint32_t saddr, ret; uint32_t saddr, ret;
@ -97,7 +99,7 @@ static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
} }
static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val) uint64_t val, unsigned size)
{ {
SLAVIO_CPUINTCTLState *s = opaque; SLAVIO_CPUINTCTLState *s = opaque;
uint32_t saddr; uint32_t saddr;
@ -122,16 +124,14 @@ static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = { static const MemoryRegionOps slavio_intctl_mem_ops = {
NULL, .read = slavio_intctl_mem_readl,
NULL, .write = slavio_intctl_mem_writel,
slavio_intctl_mem_readl, .endianness = DEVICE_NATIVE_ENDIAN,
}; .valid = {
.min_access_size = 4,
static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = { .max_access_size = 4,
NULL, },
NULL,
slavio_intctl_mem_writel,
}; };
// master system interrupt controller // master system interrupt controller
@ -422,8 +422,8 @@ static void slavio_intctl_reset(DeviceState *d)
static int slavio_intctl_init1(SysBusDevice *dev) static int slavio_intctl_init1(SysBusDevice *dev)
{ {
SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev); SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
int io_memory;
unsigned int i, j; unsigned int i, j;
char slave_name[45];
qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS); qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
memory_region_init_io(&s->iomem, &slavio_intctlm_mem_ops, s, memory_region_init_io(&s->iomem, &slavio_intctlm_mem_ops, s,
@ -431,14 +431,14 @@ static int slavio_intctl_init1(SysBusDevice *dev)
sysbus_init_mmio_region(dev, &s->iomem); sysbus_init_mmio_region(dev, &s->iomem);
for (i = 0; i < MAX_CPUS; i++) { for (i = 0; i < MAX_CPUS; i++) {
snprintf(slave_name, sizeof(slave_name),
"slave-interrupt-controller-%i", i);
for (j = 0; j < MAX_PILS; j++) { for (j = 0; j < MAX_PILS; j++) {
sysbus_init_irq(dev, &s->cpu_irqs[i][j]); sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
} }
io_memory = cpu_register_io_memory(slavio_intctl_mem_read, memory_region_init_io(&s->slaves[i].iomem, &slavio_intctl_mem_ops,
slavio_intctl_mem_write, &s->slaves[i], slave_name, INTCTL_SIZE);
&s->slaves[i], sysbus_init_mmio_region(dev, &s->slaves[i].iomem);
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
s->slaves[i].cpu = i; s->slaves[i].cpu = i;
s->slaves[i].master = s; s->slaves[i].master = s;
} }