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hw/m68k: QOMify the ColdFire interrupt controller 

Use type_init() and friends to adapt the ColdFire interrupt
controller to the latest QEMU device conventions.

Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
This commit is contained in:
Thomas Huth 2017-02-12 15:41:35 +01:00
parent 22f2dbe7ea
commit 88b86983f3
1 changed files with 45 additions and 5 deletions
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50
hw/m68k/mcf_intc.c
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@ -9,10 +9,16 @@
#include "qemu-common.h" #include "qemu-common.h"
#include "cpu.h" #include "cpu.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/m68k/mcf.h" #include "hw/m68k/mcf.h"
#include "exec/address-spaces.h" #include "exec/address-spaces.h"
#define TYPE_MCF_INTC "mcf-intc"
#define MCF_INTC(obj) OBJECT_CHECK(mcf_intc_state, (obj), TYPE_MCF_INTC)
typedef struct { typedef struct {
SysBusDevice parent_obj;
MemoryRegion iomem; MemoryRegion iomem;
uint64_t ipr; uint64_t ipr;
uint64_t imr; uint64_t imr;
@ -138,8 +144,10 @@ static void mcf_intc_set_irq(void *opaque, int irq, int level)
mcf_intc_update(s); mcf_intc_update(s);
} }
static void mcf_intc_reset(mcf_intc_state *s) static void mcf_intc_reset(DeviceState *dev)
{ {
mcf_intc_state *s = MCF_INTC(dev);
s->imr = ~0ull; s->imr = ~0ull;
s->ipr = 0; s->ipr = 0;
s->ifr = 0; s->ifr = 0;
@ -154,17 +162,49 @@ static const MemoryRegionOps mcf_intc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN, .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static void mcf_intc_instance_init(Object *obj)
{
mcf_intc_state *s = MCF_INTC(obj);
memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
}
static void mcf_intc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->reset = mcf_intc_reset;
}
static const TypeInfo mcf_intc_gate_info = {
.name = TYPE_MCF_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(mcf_intc_state),
.instance_init = mcf_intc_instance_init,
.class_init = mcf_intc_class_init,
};
static void mcf_intc_register_types(void)
{
type_register_static(&mcf_intc_gate_info);
}
type_init(mcf_intc_register_types)
qemu_irq *mcf_intc_init(MemoryRegion *sysmem, qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
hwaddr base, hwaddr base,
M68kCPU *cpu) M68kCPU *cpu)
{ {
DeviceState *dev;
mcf_intc_state *s; mcf_intc_state *s;
s = g_malloc0(sizeof(mcf_intc_state)); dev = qdev_create(NULL, TYPE_MCF_INTC);
s->cpu = cpu; qdev_init_nofail(dev);
mcf_intc_reset(s);
s = MCF_INTC(dev);
s->cpu = cpu;
memory_region_init_io(&s->iomem, NULL, &mcf_intc_ops, s, "mcf", 0x100);
memory_region_add_subregion(sysmem, base, &s->iomem); memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64); return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);