mirror of https://github.com/xqemu/xqemu.git
spapr: introduce a fixed IRQ number space
This proposal introduces a new IRQ number space layout using static numbers for all devices, depending on a device index, and a bitmap allocator for the MSI IRQ numbers which are negotiated by the guest at runtime. As the VIO device model does not have a device index but a "reg" property, we introduce a formula to compute an IRQ number from a "reg" value. It should minimize most of the collisions. The previous layout is kept in pre-3.1 machines raising the 'legacy_irq_allocation' machine class flag. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
d45360d93d
commit
82cffa2eb2
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@ -4,7 +4,7 @@ obj-y += ppc.o ppc_booke.o fdt.o
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obj-$(CONFIG_PSERIES) += spapr.o spapr_caps.o spapr_vio.o spapr_events.o
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obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o spapr_rtas.o
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obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
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obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o
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obj-$(CONFIG_PSERIES) += spapr_cpu_core.o spapr_ovec.o spapr_irq.o
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# IBM PowerNV
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obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o pnv_occ.o pnv_bmc.o
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ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
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@ -189,6 +189,11 @@ static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
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sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
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Error *local_err = NULL;
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/* Initialize the MSI IRQ allocator. */
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if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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spapr_irq_msi_init(spapr, XICS_IRQ_BASE + nr_irqs - SPAPR_IRQ_MSI);
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}
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if (kvm_enabled()) {
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if (machine_kernel_irqchip_allowed(machine) &&
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!xics_kvm_init(spapr, &local_err)) {
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@ -1636,6 +1641,10 @@ static void spapr_machine_reset(void)
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ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
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}
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if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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spapr_irq_msi_reset(spapr);
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}
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qemu_devices_reset();
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/* DRC reset may cause a device to be unplugged. This will cause troubles
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@ -1910,6 +1919,24 @@ static const VMStateDescription vmstate_spapr_patb_entry = {
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},
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};
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static bool spapr_irq_map_needed(void *opaque)
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{
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sPAPRMachineState *spapr = opaque;
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return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
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}
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static const VMStateDescription vmstate_spapr_irq_map = {
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.name = "spapr_irq_map",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = spapr_irq_map_needed,
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.fields = (VMStateField[]) {
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VMSTATE_BITMAP(irq_map, sPAPRMachineState, 0, irq_map_nr),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_spapr = {
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.name = "spapr",
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.version_id = 3,
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@ -1937,6 +1964,7 @@ static const VMStateDescription vmstate_spapr = {
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&vmstate_spapr_cap_cfpc,
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&vmstate_spapr_cap_sbbc,
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&vmstate_spapr_cap_ibs,
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&vmstate_spapr_irq_map,
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NULL
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}
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};
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@ -4086,8 +4114,12 @@ static void spapr_machine_3_0_instance_options(MachineState *machine)
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static void spapr_machine_3_0_class_options(MachineClass *mc)
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{
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sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
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spapr_machine_3_1_class_options(mc);
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SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_3_0);
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smc->legacy_irq_allocation = true;
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}
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DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
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@ -707,9 +707,11 @@ void spapr_clear_pending_events(sPAPRMachineState *spapr)
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void spapr_events_init(sPAPRMachineState *spapr)
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{
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int epow_irq;
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int epow_irq = SPAPR_IRQ_EPOW;
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epow_irq = spapr_irq_findone(spapr, &error_fatal);
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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epow_irq = spapr_irq_findone(spapr, &error_fatal);
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}
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spapr_irq_claim(spapr, epow_irq, false, &error_fatal);
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@ -729,9 +731,11 @@ void spapr_events_init(sPAPRMachineState *spapr)
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* checking that it's enabled.
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*/
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if (spapr->use_hotplug_event_source) {
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int hp_irq;
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int hp_irq = SPAPR_IRQ_HOTPLUG;
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hp_irq = spapr_irq_findone(spapr, &error_fatal);
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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hp_irq = spapr_irq_findone(spapr, &error_fatal);
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}
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spapr_irq_claim(spapr, hp_irq, false, &error_fatal);
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@ -0,0 +1,56 @@
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/*
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* QEMU PowerPC sPAPR IRQ interface
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/xics.h"
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void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
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{
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spapr->irq_map_nr = nr_msis;
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spapr->irq_map = bitmap_new(spapr->irq_map_nr);
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}
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int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
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Error **errp)
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{
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int irq;
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/*
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* The 'align_mask' parameter of bitmap_find_next_zero_area()
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* should be one less than a power of 2; 0 means no
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* alignment. Adapt the 'align' value of the former allocator
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* to fit the requirements of bitmap_find_next_zero_area()
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*/
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align -= 1;
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irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
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align);
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if (irq == spapr->irq_map_nr) {
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error_setg(errp, "can't find a free %d-IRQ block", num);
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return -1;
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}
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bitmap_set(spapr->irq_map, irq, num);
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return irq + SPAPR_IRQ_MSI;
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}
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void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
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{
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bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
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}
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void spapr_irq_msi_reset(sPAPRMachineState *spapr)
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{
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bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
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}
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@ -334,6 +334,9 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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return;
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}
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if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
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}
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spapr_irq_free(spapr, msi->first_irq, msi->num);
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if (msi_present(pdev)) {
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spapr_msi_setmsg(pdev, 0, false, 0, 0);
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@ -372,7 +375,13 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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}
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/* Allocate MSIs */
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irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, &err);
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI,
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&err);
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} else {
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irq = spapr_irq_msi_alloc(spapr, req_num,
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ret_intr_type == RTAS_TYPE_MSI, &err);
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}
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if (err) {
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error_reportf_err(err, "Can't allocate MSIs for device %x: ",
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config_addr);
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@ -392,6 +401,9 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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/* Release previous MSIs */
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if (msi) {
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if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
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}
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spapr_irq_free(spapr, msi->first_irq, msi->num);
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g_hash_table_remove(phb->msi, &config_addr);
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}
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@ -1705,14 +1717,16 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
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/* Initialize the LSI table */
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for (i = 0; i < PCI_NUM_PINS; i++) {
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uint32_t irq;
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uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
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Error *local_err = NULL;
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irq = spapr_irq_findone(spapr, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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error_prepend(errp, "can't allocate LSIs: ");
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return;
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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irq = spapr_irq_findone(spapr, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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error_prepend(errp, "can't allocate LSIs: ");
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return;
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}
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}
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spapr_irq_claim(spapr, irq, true, &local_err);
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@ -2123,6 +2137,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb,
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_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
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_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
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_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
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/* TODO: fine tune the total count of allocatable MSIs per PHB */
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_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR));
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/* Dynamic DMA window */
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@ -37,12 +37,13 @@
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/spapr_vio.h"
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#include "hw/ppc/xics.h"
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#include "hw/ppc/fdt.h"
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#include "trace.h"
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#include <libfdt.h>
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#define SPAPR_VIO_REG_BASE 0x71000000
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static void spapr_vio_get_irq(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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@ -445,6 +446,55 @@ static void spapr_vio_busdev_reset(DeviceState *qdev)
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}
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}
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/*
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* The register property of a VIO device is defined in livirt using
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* 0x1000 as a base register number plus a 0x1000 increment. For the
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* VIO tty device, the base number is changed to 0x30000000. QEMU uses
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* a base register number of 0x71000000 and then a simple increment.
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*
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* The formula below tries to compute a unique index number from the
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* register value that will be used to define the IRQ number of the
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* VIO device.
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*
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* A maximum of 256 VIO devices is covered. Collisions are possible
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* but they will be detected when the IRQ is claimed.
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*/
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static inline uint32_t spapr_vio_reg_to_irq(uint32_t reg)
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{
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uint32_t irq;
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if (reg >= SPAPR_VIO_REG_BASE) {
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/*
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* VIO device register values when allocated by QEMU. For
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* these, we simply mask the high bits to fit the overall
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* range: [0x00 - 0xff].
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*
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* The nvram VIO device (reg=0x71000000) is a static device of
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* the pseries machine and so is always allocated by QEMU. Its
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* IRQ number is 0x0.
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*/
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irq = reg & 0xff;
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} else if (reg >= 0x30000000) {
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/*
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* VIO tty devices register values, when allocated by livirt,
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* are mapped in range [0xf0 - 0xff], gives us a maximum of 16
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* vtys.
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*/
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irq = 0xf0 | ((reg >> 12) & 0xf);
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} else {
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/*
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* Other VIO devices register values, when allocated by
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* livirt, should be mapped in range [0x00 - 0xef]. Conflicts
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* will be detected when IRQ is claimed.
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*/
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irq = (reg >> 12) & 0xff;
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}
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return SPAPR_IRQ_VIO | irq;
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}
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static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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@ -485,10 +535,14 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
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}
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if (!dev->irq) {
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dev->irq = spapr_irq_findone(spapr, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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dev->irq = spapr_vio_reg_to_irq(dev->reg);
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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dev->irq = spapr_irq_findone(spapr, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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}
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@ -557,7 +611,7 @@ VIOsPAPRBus *spapr_vio_bus_init(void)
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/* Create bus on bridge device */
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qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
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bus = SPAPR_VIO_BUS(qbus);
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bus->next_reg = 0x71000000;
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bus->next_reg = SPAPR_VIO_REG_BASE;
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/* hcall-vio */
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spapr_register_hypercall(H_VIO_SIGNAL, h_vio_signal);
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@ -8,6 +8,7 @@
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#include "hw/ppc/spapr_drc.h"
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#include "hw/mem/pc-dimm.h"
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#include "hw/ppc/spapr_ovec.h"
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#include "hw/ppc/spapr_irq.h"
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struct VIOsPAPRBus;
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struct sPAPRPHBState;
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@ -101,6 +102,8 @@ struct sPAPRMachineClass {
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bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
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bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
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bool pre_2_10_has_unused_icps;
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bool legacy_irq_allocation;
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void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
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uint64_t *buid, hwaddr *pio,
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hwaddr *mmio32, hwaddr *mmio64,
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@ -167,6 +170,8 @@ struct sPAPRMachineState {
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char *kvm_type;
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const char *icp_type;
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int32_t irq_map_nr;
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unsigned long *irq_map;
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bool cmd_line_caps[SPAPR_CAP_NUM];
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sPAPRCapabilities def, eff, mig;
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@ -0,0 +1,32 @@
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/*
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* QEMU PowerPC sPAPR IRQ backend definitions
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef HW_SPAPR_IRQ_H
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#define HW_SPAPR_IRQ_H
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/*
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* IRQ range offsets per device type
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*/
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#define SPAPR_IRQ_EPOW 0x1000 /* XICS_IRQ_BASE offset */
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#define SPAPR_IRQ_HOTPLUG 0x1001
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#define SPAPR_IRQ_VIO 0x1100 /* 256 VIO devices */
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#define SPAPR_IRQ_PCI_LSI 0x1200 /* 32+ PHBs devices */
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#define SPAPR_IRQ_MSI 0x1300 /* Offset of the dynamic range covered
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* by the bitmap allocator */
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typedef struct sPAPRMachineState sPAPRMachineState;
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void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis);
|
||||
int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
|
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Error **errp);
|
||||
void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num);
|
||||
void spapr_irq_msi_reset(sPAPRMachineState *spapr);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue