mirror of https://github.com/xqemu/xqemu.git
suppressed m48t08 RTC - simplified m48t59 RTC api
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1573 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
48b2c19353
commit
819385c58b
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@ -305,7 +305,8 @@ VL_OBJS+= fdc.o mc146818rtc.o serial.o m48t59.o
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VL_OBJS+= cirrus_vga.o parallel.o
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VL_OBJS+= magic-load.o
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else
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VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t08.o magic-load.o slavio_intctl.o slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o
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VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t59.o magic-load.o slavio_intctl.o
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VL_OBJS+= slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o
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endif
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endif
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ifdef CONFIG_GDBSTUB
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356
hw/m48t08.c
356
hw/m48t08.c
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@ -1,356 +0,0 @@
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/*
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* QEMU M48T08 NVRAM emulation for Sparc platform
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*
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* Copyright (c) 2003-2004 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#include "m48t08.h"
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//#define DEBUG_NVRAM
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
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#else
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#define NVRAM_PRINTF(fmt, args...) do { } while (0)
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#endif
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#define NVRAM_MAX_MEM 0x1ff0
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#define NVRAM_MAXADDR 0x1fff
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struct m48t08_t {
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/* RTC management */
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time_t time_offset;
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time_t stop_time;
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/* NVRAM storage */
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uint8_t *buffer;
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};
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/* Fake timer functions */
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/* Generic helpers for BCD */
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static inline uint8_t toBCD (uint8_t value)
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{
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return (((value / 10) % 10) << 4) | (value % 10);
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}
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static inline uint8_t fromBCD (uint8_t BCD)
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{
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return ((BCD >> 4) * 10) + (BCD & 0x0F);
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}
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/* RTC management helpers */
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static void get_time (m48t08_t *NVRAM, struct tm *tm)
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{
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time_t t;
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t = time(NULL) + NVRAM->time_offset;
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#ifdef _WIN32
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memcpy(tm,localtime(&t),sizeof(*tm));
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#else
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localtime_r (&t, tm) ;
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#endif
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}
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static void set_time (m48t08_t *NVRAM, struct tm *tm)
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{
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time_t now, new_time;
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new_time = mktime(tm);
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now = time(NULL);
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NVRAM->time_offset = new_time - now;
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}
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/* Direct access to NVRAM */
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void m48t08_write (m48t08_t *NVRAM, uint32_t addr, uint8_t val)
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{
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struct tm tm;
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int tmp;
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addr &= NVRAM_MAXADDR;
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switch (addr) {
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case 0x1FF8:
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/* control */
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NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
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break;
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case 0x1FF9:
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/* seconds (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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tm.tm_sec = tmp;
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set_time(NVRAM, &tm);
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}
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if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
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if (val & 0x80) {
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NVRAM->stop_time = time(NULL);
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} else {
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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}
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}
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NVRAM->buffer[0x1FF9] = val & 0x80;
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break;
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case 0x1FFA:
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/* minutes (BCD) */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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tm.tm_min = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFB:
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/* hours (BCD) */
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tmp = fromBCD(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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get_time(NVRAM, &tm);
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tm.tm_hour = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFC:
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/* day of the week / century */
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tmp = fromBCD(val & 0x07);
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get_time(NVRAM, &tm);
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tm.tm_wday = tmp;
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set_time(NVRAM, &tm);
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NVRAM->buffer[0x1FFC] = val & 0x40;
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break;
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case 0x1FFD:
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/* date */
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tmp = fromBCD(val & 0x1F);
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if (tmp != 0) {
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get_time(NVRAM, &tm);
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tm.tm_mday = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFE:
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/* month */
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tmp = fromBCD(val & 0x1F);
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if (tmp >= 1 && tmp <= 12) {
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get_time(NVRAM, &tm);
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tm.tm_mon = tmp - 1;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFF:
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/* year */
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tmp = fromBCD(val);
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if (tmp >= 0 && tmp <= 99) {
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get_time(NVRAM, &tm);
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tm.tm_year = fromBCD(val);
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set_time(NVRAM, &tm);
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}
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break;
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default:
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NVRAM->buffer[addr] = val & 0xFF;
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break;
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}
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}
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uint8_t m48t08_read (m48t08_t *NVRAM, uint32_t addr)
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{
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struct tm tm;
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uint8_t retval = 0xFF;
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addr &= NVRAM_MAXADDR;
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switch (addr) {
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case 0x1FF8:
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/* control */
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goto do_read;
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case 0x1FF9:
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/* seconds (BCD) */
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get_time(NVRAM, &tm);
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retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
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break;
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case 0x1FFA:
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/* minutes (BCD) */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_min);
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break;
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case 0x1FFB:
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/* hours (BCD) */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_hour);
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break;
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case 0x1FFC:
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/* day of the week / century */
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get_time(NVRAM, &tm);
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retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
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break;
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case 0x1FFD:
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/* date */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_mday);
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break;
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case 0x1FFE:
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/* month */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_mon + 1);
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break;
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case 0x1FFF:
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/* year */
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get_time(NVRAM, &tm);
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retval = toBCD(tm.tm_year);
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break;
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default:
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do_read:
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retval = NVRAM->buffer[addr];
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break;
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}
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return retval;
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}
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static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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m48t08_t *NVRAM = opaque;
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m48t08_write(NVRAM, addr, value);
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}
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static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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m48t08_t *NVRAM = opaque;
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m48t08_write(NVRAM, addr, value);
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m48t08_write(NVRAM, addr + 1, value >> 8);
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}
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static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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m48t08_t *NVRAM = opaque;
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m48t08_write(NVRAM, addr, value);
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m48t08_write(NVRAM, addr + 1, value >> 8);
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m48t08_write(NVRAM, addr + 2, value >> 16);
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m48t08_write(NVRAM, addr + 3, value >> 24);
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}
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static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
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{
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m48t08_t *NVRAM = opaque;
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uint32_t retval = 0;
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retval = m48t08_read(NVRAM, addr);
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return retval;
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}
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static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
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{
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m48t08_t *NVRAM = opaque;
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uint32_t retval = 0;
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retval = m48t08_read(NVRAM, addr) << 8;
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retval |= m48t08_read(NVRAM, addr + 1);
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return retval;
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}
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static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
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{
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m48t08_t *NVRAM = opaque;
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uint32_t retval = 0;
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retval = m48t08_read(NVRAM, addr) << 24;
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retval |= m48t08_read(NVRAM, addr + 1) << 16;
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retval |= m48t08_read(NVRAM, addr + 2) << 8;
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retval |= m48t08_read(NVRAM, addr + 3);
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return retval;
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}
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static CPUWriteMemoryFunc *nvram_write[] = {
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&nvram_writeb,
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&nvram_writew,
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&nvram_writel,
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};
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static CPUReadMemoryFunc *nvram_read[] = {
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&nvram_readb,
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&nvram_readw,
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&nvram_readl,
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};
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static void nvram_save(QEMUFile *f, void *opaque)
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{
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m48t08_t *s = opaque;
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qemu_put_be32s(f, (uint32_t *)&s->time_offset);
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qemu_put_be32s(f, (uint32_t *)&s->stop_time);
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qemu_put_buffer(f, s->buffer, 0x2000);
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}
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static int nvram_load(QEMUFile *f, void *opaque, int version_id)
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{
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m48t08_t *s = opaque;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_be32s(f, (uint32_t *)&s->time_offset);
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qemu_get_be32s(f, (uint32_t *)&s->stop_time);
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qemu_get_buffer(f, s->buffer, 0x2000);
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return 0;
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}
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static void m48t08_reset(void *opaque)
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{
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m48t08_t *s = opaque;
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s->time_offset = 0;
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s->stop_time = 0;
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}
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/* Initialisation routine */
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m48t08_t *m48t08_init(uint32_t mem_base, uint16_t size)
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{
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m48t08_t *s;
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int mem_index;
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s = qemu_mallocz(sizeof(m48t08_t));
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if (!s)
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return NULL;
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s->buffer = qemu_mallocz(size);
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if (!s->buffer) {
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qemu_free(s);
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return NULL;
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}
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if (mem_base != 0) {
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mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
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cpu_register_physical_memory(mem_base, 0x2000, mem_index);
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}
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register_savevm("nvram", mem_base, 1, nvram_save, nvram_load, s);
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qemu_register_reset(m48t08_reset, s);
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return s;
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}
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#if 0
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struct idprom
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{
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unsigned char id_format; /* Format identifier (always 0x01) */
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unsigned char id_machtype; /* Machine type */
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unsigned char id_ethaddr[6]; /* Hardware ethernet address */
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long id_date; /* Date of manufacture */
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unsigned int id_sernum:24; /* Unique serial number */
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unsigned char id_cksum; /* Checksum - xor of the data bytes */
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unsigned char reserved[16];
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};
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#endif
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10
hw/m48t08.h
10
hw/m48t08.h
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@ -1,10 +0,0 @@
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#if !defined (__M48T08_H__)
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#define __M48T08_H__
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typedef struct m48t08_t m48t08_t;
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void m48t08_write (m48t08_t *NVRAM, uint32_t addr, uint8_t val);
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uint8_t m48t08_read (m48t08_t *NVRAM, uint32_t addr);
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m48t08_t *m48t08_init(uint32_t mem_base, uint16_t size);
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#endif /* !defined (__M48T08_H__) */
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188
hw/m48t59.c
188
hw/m48t59.c
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@ -1,7 +1,7 @@
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/*
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* QEMU M48T59 NVRAM emulation for PPC PREP platform
|
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
|
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*
|
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* Copyright (c) 2003-2004 Jocelyn Mayer
|
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* Copyright (c) 2003-2005 Jocelyn Mayer
|
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*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
|
|
@ -32,7 +32,14 @@
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#define NVRAM_PRINTF(fmt, args...) do { } while (0)
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#endif
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/*
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* The M48T08 and M48T59 chips are very similar. The newer '59 has
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* alarm and a watchdog timer and related control registers. In the
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* PPC platform there is also a nvram lock function.
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*/
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struct m48t59_t {
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/* Model parameters */
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int type; // 8 = m48t08, 59 = m48t59
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/* Hardware parameters */
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int IRQ;
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int mem_index;
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@ -188,14 +195,17 @@ static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
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}
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/* Direct access to NVRAM */
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void m48t59_write (m48t59_t *NVRAM, uint32_t val)
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void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val)
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{
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struct tm tm;
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int tmp;
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if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
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switch (NVRAM->addr) {
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if (addr > 0x1FF8 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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if (NVRAM->type == 8 &&
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(addr >= 0x1ff0 && addr <= 0x1ff7))
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goto do_write;
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switch (addr) {
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case 0x1FF0:
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/* flags register : read-only */
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break;
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|
|
@ -204,52 +214,52 @@ void m48t59_write (m48t59_t *NVRAM, uint32_t val)
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break;
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case 0x1FF2:
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/* alarm seconds */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_alarm(NVRAM, &tm);
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tm.tm_sec = tmp;
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM, &tm);
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}
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_alarm(NVRAM, &tm);
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tm.tm_sec = tmp;
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM, &tm);
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}
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break;
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case 0x1FF3:
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/* alarm minutes */
|
||||
tmp = fromBCD(val & 0x7F);
|
||||
if (tmp >= 0 && tmp <= 59) {
|
||||
get_alarm(NVRAM, &tm);
|
||||
tm.tm_min = tmp;
|
||||
NVRAM->buffer[0x1FF3] = val;
|
||||
set_alarm(NVRAM, &tm);
|
||||
}
|
||||
tmp = fromBCD(val & 0x7F);
|
||||
if (tmp >= 0 && tmp <= 59) {
|
||||
get_alarm(NVRAM, &tm);
|
||||
tm.tm_min = tmp;
|
||||
NVRAM->buffer[0x1FF3] = val;
|
||||
set_alarm(NVRAM, &tm);
|
||||
}
|
||||
break;
|
||||
case 0x1FF4:
|
||||
/* alarm hours */
|
||||
tmp = fromBCD(val & 0x3F);
|
||||
if (tmp >= 0 && tmp <= 23) {
|
||||
get_alarm(NVRAM, &tm);
|
||||
tm.tm_hour = tmp;
|
||||
NVRAM->buffer[0x1FF4] = val;
|
||||
set_alarm(NVRAM, &tm);
|
||||
}
|
||||
tmp = fromBCD(val & 0x3F);
|
||||
if (tmp >= 0 && tmp <= 23) {
|
||||
get_alarm(NVRAM, &tm);
|
||||
tm.tm_hour = tmp;
|
||||
NVRAM->buffer[0x1FF4] = val;
|
||||
set_alarm(NVRAM, &tm);
|
||||
}
|
||||
break;
|
||||
case 0x1FF5:
|
||||
/* alarm date */
|
||||
tmp = fromBCD(val & 0x1F);
|
||||
if (tmp != 0) {
|
||||
get_alarm(NVRAM, &tm);
|
||||
tm.tm_mday = tmp;
|
||||
NVRAM->buffer[0x1FF5] = val;
|
||||
set_alarm(NVRAM, &tm);
|
||||
}
|
||||
tmp = fromBCD(val & 0x1F);
|
||||
if (tmp != 0) {
|
||||
get_alarm(NVRAM, &tm);
|
||||
tm.tm_mday = tmp;
|
||||
NVRAM->buffer[0x1FF5] = val;
|
||||
set_alarm(NVRAM, &tm);
|
||||
}
|
||||
break;
|
||||
case 0x1FF6:
|
||||
/* interrupts */
|
||||
NVRAM->buffer[0x1FF6] = val;
|
||||
NVRAM->buffer[0x1FF6] = val;
|
||||
break;
|
||||
case 0x1FF7:
|
||||
/* watchdog */
|
||||
NVRAM->buffer[0x1FF7] = val;
|
||||
set_up_watchdog(NVRAM, val);
|
||||
NVRAM->buffer[0x1FF7] = val;
|
||||
set_up_watchdog(NVRAM, val);
|
||||
break;
|
||||
case 0x1FF8:
|
||||
/* control */
|
||||
|
|
@ -328,24 +338,27 @@ void m48t59_write (m48t59_t *NVRAM, uint32_t val)
|
|||
break;
|
||||
default:
|
||||
/* Check lock registers state */
|
||||
if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
|
||||
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
|
||||
break;
|
||||
if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
|
||||
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
|
||||
break;
|
||||
if (NVRAM->addr < 0x1FF0 ||
|
||||
(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
|
||||
NVRAM->buffer[NVRAM->addr] = val & 0xFF;
|
||||
do_write:
|
||||
if (addr < NVRAM->size) {
|
||||
NVRAM->buffer[addr] = val & 0xFF;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t m48t59_read (m48t59_t *NVRAM)
|
||||
uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr)
|
||||
{
|
||||
struct tm tm;
|
||||
uint32_t retval = 0xFF;
|
||||
|
||||
switch (NVRAM->addr) {
|
||||
if (NVRAM->type == 8 &&
|
||||
(addr >= 0x1ff0 && addr <= 0x1ff7))
|
||||
goto do_read;
|
||||
switch (addr) {
|
||||
case 0x1FF0:
|
||||
/* flags register */
|
||||
goto do_read;
|
||||
|
|
@ -412,19 +425,18 @@ uint32_t m48t59_read (m48t59_t *NVRAM)
|
|||
break;
|
||||
default:
|
||||
/* Check lock registers state */
|
||||
if (NVRAM->addr >= 0x20 && NVRAM->addr <= 0x2F && (NVRAM->lock & 1))
|
||||
if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
|
||||
break;
|
||||
if (NVRAM->addr >= 0x30 && NVRAM->addr <= 0x3F && (NVRAM->lock & 2))
|
||||
if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
|
||||
break;
|
||||
if (NVRAM->addr < 0x1FF0 ||
|
||||
(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
|
||||
do_read:
|
||||
retval = NVRAM->buffer[NVRAM->addr];
|
||||
do_read:
|
||||
if (addr < NVRAM->size) {
|
||||
retval = NVRAM->buffer[addr];
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000)
|
||||
NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
|
||||
if (addr > 0x1FF9 && addr < 0x2000)
|
||||
NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr, retval);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
|
@ -456,7 +468,7 @@ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
|
|||
NVRAM->addr |= val << 8;
|
||||
break;
|
||||
case 3:
|
||||
m48t59_write(NVRAM, val);
|
||||
m48t59_write(NVRAM, val, NVRAM->addr);
|
||||
NVRAM->addr = 0x0000;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -472,7 +484,7 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
|
|||
addr -= NVRAM->io_base;
|
||||
switch (addr) {
|
||||
case 3:
|
||||
retval = m48t59_read(NVRAM);
|
||||
retval = m48t59_read(NVRAM, NVRAM->addr);
|
||||
break;
|
||||
default:
|
||||
retval = -1;
|
||||
|
|
@ -488,8 +500,7 @@ static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|||
m48t59_t *NVRAM = opaque;
|
||||
|
||||
addr -= NVRAM->mem_base;
|
||||
if (addr < 0x1FF0)
|
||||
NVRAM->buffer[addr] = value;
|
||||
m48t59_write(NVRAM, addr, value & 0xff);
|
||||
}
|
||||
|
||||
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
|
||||
|
|
@ -497,10 +508,8 @@ static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|||
m48t59_t *NVRAM = opaque;
|
||||
|
||||
addr -= NVRAM->mem_base;
|
||||
if (addr < 0x1FF0) {
|
||||
NVRAM->buffer[addr] = value >> 8;
|
||||
NVRAM->buffer[addr + 1] = value;
|
||||
}
|
||||
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
|
||||
m48t59_write(NVRAM, addr + 1, value & 0xff);
|
||||
}
|
||||
|
||||
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
||||
|
|
@ -508,53 +517,43 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
|
|||
m48t59_t *NVRAM = opaque;
|
||||
|
||||
addr -= NVRAM->mem_base;
|
||||
if (addr < 0x1FF0) {
|
||||
NVRAM->buffer[addr] = value >> 24;
|
||||
NVRAM->buffer[addr + 1] = value >> 16;
|
||||
NVRAM->buffer[addr + 2] = value >> 8;
|
||||
NVRAM->buffer[addr + 3] = value;
|
||||
}
|
||||
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
|
||||
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
|
||||
m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
|
||||
m48t59_write(NVRAM, addr + 3, value & 0xff);
|
||||
}
|
||||
|
||||
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
m48t59_t *NVRAM = opaque;
|
||||
uint32_t retval = 0;
|
||||
uint32_t retval;
|
||||
|
||||
addr -= NVRAM->mem_base;
|
||||
if (addr < 0x1FF0)
|
||||
retval = NVRAM->buffer[addr];
|
||||
|
||||
retval = m48t59_read(NVRAM, addr);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
m48t59_t *NVRAM = opaque;
|
||||
uint32_t retval = 0;
|
||||
uint32_t retval;
|
||||
|
||||
addr -= NVRAM->mem_base;
|
||||
if (addr < 0x1FF0) {
|
||||
retval = NVRAM->buffer[addr] << 8;
|
||||
retval |= NVRAM->buffer[addr + 1];
|
||||
}
|
||||
|
||||
retval = m48t59_read(NVRAM, addr) << 8;
|
||||
retval |= m48t59_read(NVRAM, addr + 1);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
m48t59_t *NVRAM = opaque;
|
||||
uint32_t retval = 0;
|
||||
|
||||
addr -= NVRAM->mem_base;
|
||||
if (addr < 0x1FF0) {
|
||||
retval = NVRAM->buffer[addr] << 24;
|
||||
retval |= NVRAM->buffer[addr + 1] << 16;
|
||||
retval |= NVRAM->buffer[addr + 2] << 8;
|
||||
retval |= NVRAM->buffer[addr + 3];
|
||||
}
|
||||
uint32_t retval;
|
||||
|
||||
addr -= NVRAM->mem_base;
|
||||
retval = m48t59_read(NVRAM, addr) << 24;
|
||||
retval |= m48t59_read(NVRAM, addr + 1) << 16;
|
||||
retval |= m48t59_read(NVRAM, addr + 2) << 8;
|
||||
retval |= m48t59_read(NVRAM, addr + 3);
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
@ -569,9 +568,11 @@ static CPUReadMemoryFunc *nvram_read[] = {
|
|||
&nvram_readw,
|
||||
&nvram_readl,
|
||||
};
|
||||
|
||||
/* Initialisation routine */
|
||||
m48t59_t *m48t59_init (int IRQ, uint32_t mem_base,
|
||||
uint32_t io_base, uint16_t size)
|
||||
m48t59_t *m48t59_init (int IRQ, target_ulong mem_base,
|
||||
uint32_t io_base, uint16_t size,
|
||||
int type)
|
||||
{
|
||||
m48t59_t *s;
|
||||
|
||||
|
|
@ -588,14 +589,19 @@ m48t59_t *m48t59_init (int IRQ, uint32_t mem_base,
|
|||
s->mem_base = mem_base;
|
||||
s->io_base = io_base;
|
||||
s->addr = 0;
|
||||
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
|
||||
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
|
||||
s->type = type;
|
||||
if (io_base != 0) {
|
||||
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
|
||||
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
|
||||
}
|
||||
if (mem_base != 0) {
|
||||
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
|
||||
cpu_register_physical_memory(mem_base, 0x4000, s->mem_index);
|
||||
}
|
||||
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
|
||||
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
|
||||
if (type == 59) {
|
||||
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
|
||||
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
|
||||
}
|
||||
s->lock = 0;
|
||||
|
||||
return s;
|
||||
|
|
|
|||
10
hw/m48t59.h
10
hw/m48t59.h
|
|
@ -3,11 +3,11 @@
|
|||
|
||||
typedef struct m48t59_t m48t59_t;
|
||||
|
||||
void m48t59_write (m48t59_t *NVRAM, uint32_t val);
|
||||
uint32_t m48t59_read (m48t59_t *NVRAM);
|
||||
void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr);
|
||||
void m48t59_write (m48t59_t *NVRAM, uint32_t addr, uint32_t val);
|
||||
uint32_t m48t59_read (m48t59_t *NVRAM, uint32_t addr);
|
||||
void m48t59_toggle_lock (m48t59_t *NVRAM, int lock);
|
||||
m48t59_t *m48t59_init (int IRQ, uint32_t io_base,
|
||||
uint32_t mem_base, uint16_t size);
|
||||
m48t59_t *m48t59_init (int IRQ, target_ulong mem_base,
|
||||
uint32_t io_base, uint16_t size,
|
||||
int type);
|
||||
|
||||
#endif /* !defined (__M48T59_H__) */
|
||||
|
|
|
|||
50
hw/ppc.c
50
hw/ppc.c
|
|
@ -283,61 +283,45 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
|
|||
/* NVRAM helpers */
|
||||
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
|
||||
{
|
||||
m48t59_set_addr(nvram, addr);
|
||||
m48t59_write(nvram, value);
|
||||
m48t59_write(nvram, addr, value);
|
||||
}
|
||||
|
||||
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
|
||||
{
|
||||
m48t59_set_addr(nvram, addr);
|
||||
return m48t59_read(nvram);
|
||||
return m48t59_read(nvram, addr);
|
||||
}
|
||||
|
||||
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
||||
{
|
||||
m48t59_set_addr(nvram, addr);
|
||||
m48t59_write(nvram, value >> 8);
|
||||
m48t59_set_addr(nvram, addr + 1);
|
||||
m48t59_write(nvram, value & 0xFF);
|
||||
m48t59_write(nvram, addr, value >> 8);
|
||||
m48t59_write(nvram, addr + 1, value & 0xFF);
|
||||
}
|
||||
|
||||
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
|
||||
{
|
||||
uint16_t tmp;
|
||||
|
||||
m48t59_set_addr(nvram, addr);
|
||||
tmp = m48t59_read(nvram) << 8;
|
||||
m48t59_set_addr(nvram, addr + 1);
|
||||
tmp |= m48t59_read(nvram);
|
||||
|
||||
tmp = m48t59_read(nvram, addr) << 8;
|
||||
tmp |= m48t59_read(nvram, addr + 1);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
||||
{
|
||||
m48t59_set_addr(nvram, addr);
|
||||
m48t59_write(nvram, value >> 24);
|
||||
m48t59_set_addr(nvram, addr + 1);
|
||||
m48t59_write(nvram, (value >> 16) & 0xFF);
|
||||
m48t59_set_addr(nvram, addr + 2);
|
||||
m48t59_write(nvram, (value >> 8) & 0xFF);
|
||||
m48t59_set_addr(nvram, addr + 3);
|
||||
m48t59_write(nvram, value & 0xFF);
|
||||
m48t59_write(nvram, addr, value >> 24);
|
||||
m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
|
||||
m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
|
||||
m48t59_write(nvram, addr + 3, value & 0xFF);
|
||||
}
|
||||
|
||||
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
m48t59_set_addr(nvram, addr);
|
||||
tmp = m48t59_read(nvram) << 24;
|
||||
m48t59_set_addr(nvram, addr + 1);
|
||||
tmp |= m48t59_read(nvram) << 16;
|
||||
m48t59_set_addr(nvram, addr + 2);
|
||||
tmp |= m48t59_read(nvram) << 8;
|
||||
m48t59_set_addr(nvram, addr + 3);
|
||||
tmp |= m48t59_read(nvram);
|
||||
|
||||
tmp = m48t59_read(nvram, addr) << 24;
|
||||
tmp |= m48t59_read(nvram, addr + 1) << 16;
|
||||
tmp |= m48t59_read(nvram, addr + 2) << 8;
|
||||
tmp |= m48t59_read(nvram, addr + 3);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
|
|
@ -347,11 +331,9 @@ void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
|||
int i;
|
||||
|
||||
for (i = 0; i < max && str[i] != '\0'; i++) {
|
||||
m48t59_set_addr(nvram, addr + i);
|
||||
m48t59_write(nvram, str[i]);
|
||||
m48t59_write(nvram, addr + i, str[i]);
|
||||
}
|
||||
m48t59_set_addr(nvram, addr + max - 1);
|
||||
m48t59_write(nvram, '\0');
|
||||
m48t59_write(nvram, addr + max - 1, '\0');
|
||||
}
|
||||
|
||||
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
|
||||
|
|
|
|||
|
|
@ -449,7 +449,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
|
||||
macio_init(pci_bus, 0x0017);
|
||||
|
||||
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
|
||||
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
|
||||
|
||||
arch_name = "HEATHROW";
|
||||
} else {
|
||||
|
|
@ -496,7 +496,7 @@ static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
|
||||
macio_init(pci_bus, 0x0022);
|
||||
|
||||
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE);
|
||||
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
|
||||
|
||||
arch_name = "MAC99";
|
||||
}
|
||||
|
|
|
|||
|
|
@ -652,7 +652,7 @@ static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
|
||||
#endif
|
||||
|
||||
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE);
|
||||
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
|
||||
if (nvram == NULL)
|
||||
return;
|
||||
sysctrl->nvram = nvram;
|
||||
|
|
|
|||
53
hw/sun4m.c
53
hw/sun4m.c
|
|
@ -22,7 +22,6 @@
|
|||
* THE SOFTWARE.
|
||||
*/
|
||||
#include "vl.h"
|
||||
#include "m48t08.h"
|
||||
|
||||
#define KERNEL_LOAD_ADDR 0x00004000
|
||||
#define CMDLINE_ADDR 0x007ff000
|
||||
|
|
@ -88,36 +87,36 @@ void DMA_register_channel (int nchan,
|
|||
{
|
||||
}
|
||||
|
||||
static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value)
|
||||
static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
||||
{
|
||||
m48t08_write(nvram, addr++, (value >> 8) & 0xff);
|
||||
m48t08_write(nvram, addr++, value & 0xff);
|
||||
m48t59_write(nvram, addr++, (value >> 8) & 0xff);
|
||||
m48t59_write(nvram, addr++, value & 0xff);
|
||||
}
|
||||
|
||||
static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value)
|
||||
static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
||||
{
|
||||
m48t08_write(nvram, addr++, value >> 24);
|
||||
m48t08_write(nvram, addr++, (value >> 16) & 0xff);
|
||||
m48t08_write(nvram, addr++, (value >> 8) & 0xff);
|
||||
m48t08_write(nvram, addr++, value & 0xff);
|
||||
m48t59_write(nvram, addr++, value >> 24);
|
||||
m48t59_write(nvram, addr++, (value >> 16) & 0xff);
|
||||
m48t59_write(nvram, addr++, (value >> 8) & 0xff);
|
||||
m48t59_write(nvram, addr++, value & 0xff);
|
||||
}
|
||||
|
||||
static void nvram_set_string (m48t08_t *nvram, uint32_t addr,
|
||||
static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
|
||||
const unsigned char *str, uint32_t max)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < max && str[i] != '\0'; i++) {
|
||||
m48t08_write(nvram, addr + i, str[i]);
|
||||
m48t59_write(nvram, addr + i, str[i]);
|
||||
}
|
||||
m48t08_write(nvram, addr + max - 1, '\0');
|
||||
m48t59_write(nvram, addr + max - 1, '\0');
|
||||
}
|
||||
|
||||
static m48t08_t *nvram;
|
||||
static m48t59_t *nvram;
|
||||
|
||||
extern int nographic;
|
||||
|
||||
static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,
|
||||
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
|
||||
int boot_device, uint32_t RAM_size,
|
||||
uint32_t kernel_size,
|
||||
int width, int height, int depth)
|
||||
|
|
@ -129,9 +128,9 @@ static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,
|
|||
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
|
||||
nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
|
||||
// NVRAM_size, arch not applicable
|
||||
m48t08_write(nvram, 0x2F, nographic & 0xff);
|
||||
m48t59_write(nvram, 0x2F, nographic & 0xff);
|
||||
nvram_set_lword(nvram, 0x30, RAM_size);
|
||||
m48t08_write(nvram, 0x34, boot_device & 0xff);
|
||||
m48t59_write(nvram, 0x34, boot_device & 0xff);
|
||||
nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
|
||||
nvram_set_lword(nvram, 0x3C, kernel_size);
|
||||
if (cmdline) {
|
||||
|
|
@ -146,21 +145,21 @@ static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,
|
|||
|
||||
// Sun4m specific use
|
||||
i = 0x1fd8;
|
||||
m48t08_write(nvram, i++, 0x01);
|
||||
m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
|
||||
m48t59_write(nvram, i++, 0x01);
|
||||
m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
|
||||
j = 0;
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i++, macaddr[j++]);
|
||||
m48t08_write(nvram, i, macaddr[j]);
|
||||
m48t59_write(nvram, i++, macaddr[j++]);
|
||||
m48t59_write(nvram, i++, macaddr[j++]);
|
||||
m48t59_write(nvram, i++, macaddr[j++]);
|
||||
m48t59_write(nvram, i++, macaddr[j++]);
|
||||
m48t59_write(nvram, i++, macaddr[j++]);
|
||||
m48t59_write(nvram, i, macaddr[j]);
|
||||
|
||||
/* Calculate checksum */
|
||||
for (i = 0x1fd8; i < 0x1fe7; i++) {
|
||||
tmp ^= m48t08_read(nvram, i);
|
||||
tmp ^= m48t59_read(nvram, i);
|
||||
}
|
||||
m48t08_write(nvram, 0x1fe7, tmp);
|
||||
m48t59_write(nvram, 0x1fe7, tmp);
|
||||
}
|
||||
|
||||
static void *slavio_intctl;
|
||||
|
|
@ -231,7 +230,7 @@ static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
|
||||
tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
|
||||
lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
|
||||
nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
|
||||
nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
|
||||
slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
|
||||
slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
|
||||
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
||||
|
|
|
|||
50
hw/sun4u.c
50
hw/sun4u.c
|
|
@ -68,60 +68,46 @@ void DMA_register_channel (int nchan,
|
|||
/* NVRAM helpers */
|
||||
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
|
||||
{
|
||||
m48t59_set_addr(nvram, addr);
|
||||
m48t59_write(nvram, value);
|
||||
m48t59_write(nvram, addr, value);
|
||||
}
|
||||
|
||||
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
|
||||
{
|
||||
m48t59_set_addr(nvram, addr);
|
||||
return m48t59_read(nvram);
|
||||
return m48t59_read(nvram, addr);
|
||||
}
|
||||
|
||||
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
||||
{
|
||||
m48t59_set_addr(nvram, addr);
|
||||
m48t59_write(nvram, value >> 8);
|
||||
m48t59_set_addr(nvram, addr + 1);
|
||||
m48t59_write(nvram, value & 0xFF);
|
||||
m48t59_write(nvram, addr, value >> 8);
|
||||
m48t59_write(nvram, addr + 1, value & 0xFF);
|
||||
}
|
||||
|
||||
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
|
||||
{
|
||||
uint16_t tmp;
|
||||
|
||||
m48t59_set_addr(nvram, addr);
|
||||
tmp = m48t59_read(nvram) << 8;
|
||||
m48t59_set_addr(nvram, addr + 1);
|
||||
tmp |= m48t59_read(nvram);
|
||||
tmp = m48t59_read(nvram, addr) << 8;
|
||||
tmp |= m48t59_read(nvram, addr + 1);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
||||
{
|
||||
m48t59_set_addr(nvram, addr);
|
||||
m48t59_write(nvram, value >> 24);
|
||||
m48t59_set_addr(nvram, addr + 1);
|
||||
m48t59_write(nvram, (value >> 16) & 0xFF);
|
||||
m48t59_set_addr(nvram, addr + 2);
|
||||
m48t59_write(nvram, (value >> 8) & 0xFF);
|
||||
m48t59_set_addr(nvram, addr + 3);
|
||||
m48t59_write(nvram, value & 0xFF);
|
||||
m48t59_write(nvram, addr, value >> 24);
|
||||
m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
|
||||
m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
|
||||
m48t59_write(nvram, addr + 3, value & 0xFF);
|
||||
}
|
||||
|
||||
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
m48t59_set_addr(nvram, addr);
|
||||
tmp = m48t59_read(nvram) << 24;
|
||||
m48t59_set_addr(nvram, addr + 1);
|
||||
tmp |= m48t59_read(nvram) << 16;
|
||||
m48t59_set_addr(nvram, addr + 2);
|
||||
tmp |= m48t59_read(nvram) << 8;
|
||||
m48t59_set_addr(nvram, addr + 3);
|
||||
tmp |= m48t59_read(nvram);
|
||||
tmp = m48t59_read(nvram, addr) << 24;
|
||||
tmp |= m48t59_read(nvram, addr + 1) << 16;
|
||||
tmp |= m48t59_read(nvram, addr + 2) << 8;
|
||||
tmp |= m48t59_read(nvram, addr + 3);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
|
@ -132,11 +118,9 @@ void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
|||
int i;
|
||||
|
||||
for (i = 0; i < max && str[i] != '\0'; i++) {
|
||||
m48t59_set_addr(nvram, addr + i);
|
||||
m48t59_write(nvram, str[i]);
|
||||
m48t59_write(nvram, addr + i, str[i]);
|
||||
}
|
||||
m48t59_set_addr(nvram, addr + max - 1);
|
||||
m48t59_write(nvram, '\0');
|
||||
m48t59_write(nvram, addr + max - 1, '\0');
|
||||
}
|
||||
|
||||
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
|
||||
|
|
@ -357,7 +341,7 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
|
|||
pci_cmd646_ide_init(pci_bus, bs_table, 1);
|
||||
kbd_init();
|
||||
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
|
||||
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE);
|
||||
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
|
||||
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
|
||||
KERNEL_LOAD_ADDR, kernel_size,
|
||||
kernel_cmdline,
|
||||
|
|
|
|||
Loading…
Reference in New Issue