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tcg/mips: implement movcond op on MIPS32R2 

movcond operation can be implemented on MIPS32 Release 2 using the MOVN,
MOVZ, SLT and SLTU instructions.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2012-09-21 18:20:26 +02:00
parent 04f71aa3fd
commit 7d7c4930ab
2 changed files with 77 additions and 0 deletions
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69
tcg/mips/tcg-target.c
View File

@ -308,6 +308,8 @@ enum {
OPC_SRAV = OPC_SPECIAL | 0x07, OPC_SRAV = OPC_SPECIAL | 0x07,
OPC_JR = OPC_SPECIAL | 0x08, OPC_JR = OPC_SPECIAL | 0x08,
OPC_JALR = OPC_SPECIAL | 0x09, OPC_JALR = OPC_SPECIAL | 0x09,
OPC_MOVZ = OPC_SPECIAL | 0x0A,
OPC_MOVN = OPC_SPECIAL | 0x0B,
OPC_MFHI = OPC_SPECIAL | 0x10, OPC_MFHI = OPC_SPECIAL | 0x10,
OPC_MFLO = OPC_SPECIAL | 0x12, OPC_MFLO = OPC_SPECIAL | 0x12,
OPC_MULT = OPC_SPECIAL | 0x18, OPC_MULT = OPC_SPECIAL | 0x18,
@ -735,6 +737,68 @@ static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGArg arg1,
reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr); reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr);
} }
static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
TCGArg c1, TCGArg c2, TCGArg v)
{
switch (cond) {
case TCG_COND_EQ:
if (c1 == 0) {
tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c2);
} else if (c2 == 0) {
tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c1);
} else {
tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
}
break;
case TCG_COND_NE:
if (c1 == 0) {
tcg_out_opc_reg(s, OPC_MOVN, ret, v, c2);
} else if (c2 == 0) {
tcg_out_opc_reg(s, OPC_MOVN, ret, v, c1);
} else {
tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
}
break;
case TCG_COND_LT:
tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
break;
case TCG_COND_LTU:
tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
break;
case TCG_COND_GE:
tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
break;
case TCG_COND_GEU:
tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
break;
case TCG_COND_LE:
tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
break;
case TCG_COND_LEU:
tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
break;
case TCG_COND_GT:
tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
break;
case TCG_COND_GTU:
tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
break;
default:
tcg_abort();
break;
}
}
static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
TCGArg arg1, TCGArg arg2) TCGArg arg1, TCGArg arg2)
{ {
@ -1468,6 +1532,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]); tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]);
break; break;
case INDEX_op_movcond_i32:
tcg_out_movcond(s, args[5], args[0], args[1], args[2], args[3]);
break;
case INDEX_op_setcond_i32: case INDEX_op_setcond_i32:
tcg_out_setcond(s, args[3], args[0], args[1], args[2]); tcg_out_setcond(s, args[3], args[0], args[1], args[2]);
break; break;
@ -1559,6 +1627,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_deposit_i32, { "r", "0", "rZ" } }, { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
{ INDEX_op_brcond_i32, { "rZ", "rZ" } }, { INDEX_op_brcond_i32, { "rZ", "rZ" } },
{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },

8
tcg/mips/tcg-target.h
View File

@ -86,7 +86,15 @@ typedef enum {
#define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nand_i32 0
/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
#if defined(_MIPS_ARCH_MIPS4) || defined(_MIPS_ARCH_MIPS32) || \
defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_LOONGSON2E) || \
defined(_MIPS_ARCH_LOONGSON2F)
#define TCG_TARGET_HAS_movcond_i32 1
#else
#define TCG_TARGET_HAS_movcond_i32 0 #define TCG_TARGET_HAS_movcond_i32 0
#endif
/* optional instructions only implemented on MIPS32R2 */ /* optional instructions only implemented on MIPS32R2 */
#ifdef _MIPS_ARCH_MIPS32R2 #ifdef _MIPS_ARCH_MIPS32R2