mirror of https://github.com/xqemu/xqemu.git
target-s390: Convert LPSWE
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
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fc778b55a5
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@ -627,6 +627,8 @@
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C(0xeb2f, LCTLG, RSY_a, Z, 0, a2, 0, 0, lctlg, 0)
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C(0xeb2f, LCTLG, RSY_a, Z, 0, a2, 0, 0, lctlg, 0)
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/* LOAD PSW */
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/* LOAD PSW */
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C(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0)
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C(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0)
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/* LOAD PSW EXTENDED */
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C(0xb2b2, LPSWE, S, Z, 0, a2, 0, 0, lpswe, 0)
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/* LOAD REAL ADDRESS */
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/* LOAD REAL ADDRESS */
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C(0xb100, LRA, RX_a, Z, 0, a2, r1, 0, lra, 0)
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C(0xb100, LRA, RX_a, Z, 0, a2, r1, 0, lra, 0)
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C(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0)
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C(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0)
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@ -1022,10 +1022,9 @@ static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
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uint32_t insn)
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uint32_t insn)
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{
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{
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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TCGv_i64 tmp, tmp2, tmp3;
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TCGv_i64 tmp;
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TCGv_i32 tmp32_1;
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TCGv_i32 tmp32_1;
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int r1, r2;
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int r1, r2;
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int r3, d2, b2;
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r1 = (insn >> 4) & 0xf;
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r1 = (insn >> 4) & 0xf;
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r2 = insn & 0xf;
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r2 = insn & 0xf;
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@ -1033,23 +1032,6 @@ static void disas_b2(CPUS390XState *env, DisasContext *s, int op,
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LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
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LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
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switch (op) {
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switch (op) {
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case 0xb2: /* LPSWE D2(B2) [S] */
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/* Load PSW Extended */
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check_privileged(s);
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decode_rs(s, insn, &r1, &r3, &b2, &d2);
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tmp = get_address(s, 0, b2, d2);
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tmp2 = tcg_temp_new_i64();
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tmp3 = tcg_temp_new_i64();
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tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
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tcg_gen_addi_i64(tmp, tmp, 8);
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tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
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gen_helper_load_psw(cpu_env, tmp2, tmp3);
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/* we need to keep cc_op intact */
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s->is_jmp = DISAS_JUMP;
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i64(tmp2);
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tcg_temp_free_i64(tmp3);
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break;
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case 0x20: /* SERVC R1,R2 [RRE] */
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case 0x20: /* SERVC R1,R2 [RRE] */
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/* SCLP Service call (PV hypercall) */
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/* SCLP Service call (PV hypercall) */
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check_privileged(s);
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check_privileged(s);
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@ -2254,6 +2236,23 @@ static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
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tcg_temp_free_i64(t2);
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tcg_temp_free_i64(t2);
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return EXIT_NORETURN;
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return EXIT_NORETURN;
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}
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}
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static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
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{
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TCGv_i64 t1, t2;
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check_privileged(s);
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t1 = tcg_temp_new_i64();
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t2 = tcg_temp_new_i64();
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tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
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tcg_gen_addi_i64(o->in2, o->in2, 8);
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tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
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gen_helper_load_psw(cpu_env, t1, t2);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t2);
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return EXIT_NORETURN;
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}
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#endif
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#endif
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static ExitStatus op_lam(DisasContext *s, DisasOps *o)
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static ExitStatus op_lam(DisasContext *s, DisasOps *o)
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